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* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-3/+3
| | | | | | since they are equivalent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
* Deduplicate ARM call-related instructions.Jakob Stoklund Olesen2012-04-061-3/+1
| | | | | | | | We had special instructions for iOS because r9 is call-clobbered, but that is represented dynamically by the register mask operands now, so there is no need for the pseudo-instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154144 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions.Craig Topper2012-03-251-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153421 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM BL/BLX instruction fixups should use relocations.Jim Grosbach2012-02-271-0/+2
| | | | | | | | | | | | | We on the linker to resolve calls to the appropriate BL/BLX instruction to make interworking function correctly. It uses the symbol in the relocation to do that, so we need to be careful about being too clever. To enable this for ARM mode, split the BL/BLX fixup kind off from the unconditional-branch fixups. rdar://10927209 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
* Widen the instruction encoder that TblGen emits to a 64 bits, which should ↵Owen Anderson2012-01-241-1/+1
| | | | | | accomodate every target I can think of offhand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148833 91177308-0d34-0410-b5e6-96231b3b80d8
* More dead code removal (using -Wunreachable-code)David Blaikie2012-01-201-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
* First chunk of MachineInstr bundle support.Evan Cheng2011-12-061-1/+1
| | | | | | | | | | 1. Added opcode BUNDLE 2. Taught MachineInstr class to deal with bundled MIs 3. Changed MachineBasicBlock iterator to skip over bundled MIs; added an iterator to walk all the MIs 4. Taught MachineBasicBlock methods about bundled MIs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145975 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new ARMConstantPoolSymbol class to handle external symbols.Bill Wendling2011-10-011-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140939 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch over to using ARMConstantPoolConstant for global variables, functions,Bill Wendling2011-10-011-1/+1
| | | | | | | and block addresses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140936 91177308-0d34-0410-b5e6-96231b3b80d8
* Zap some junk from the ARM instruction descriptions.Eli Friedman2011-09-131-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139575 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-091-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDRD(immediate).Jim Grosbach2011-09-081-0/+2
| | | | | | Refactor operand handling for STRD as well. Tests for that forthcoming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Formatting.Jim Grosbach2011-09-021-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139024 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve encoding support for BLX with immediat eoperands, and fix a BLX ↵Owen Anderson2011-08-261-0/+2
| | | | | | decoding bug this uncovered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM clean up the imm_sr operand class representation.Jim Grosbach2011-08-171-2/+0
| | | | | | | | | | Represent the operand value as it will be encoded in the instruction. This allows removing the specialized encoder and decoder methods entirely. Add an assembler match class while we're at it to lay groundwork for parsing the thumb shift instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137879 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encodings for Thumb ASR and LSR immediate operands. They encode the ↵Owen Anderson2011-08-081-0/+2
| | | | | | range 1-32, with 32 encoded as 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137062 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM refactoring assembly parsing of memory address operands.Jim Grosbach2011-08-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Memory operand parsing is a bit haphazzard at the moment, in no small part due to the even more haphazzard representations of memory operands in the .td files. Start cleaning that all up, at least a bit. The addressing modes in the .td files will be being simplified to not be so monolithic, especially with regards to immediate vs. register offsets and post-indexed addressing. addrmode3 is on its way with this patch, for example. This patch is foundational to enable going back to smaller incremental patches for the individual memory referencing instructions themselves. It does just enough to get the basics in place and handle the "make check" regression tests we already have. Follow-up work will be fleshing out the details and adding more robust test cases for the individual instructions, starting with ARM mode and moving from there into Thumb and Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM parsing and encoding of SBFX and UBFX.Jim Grosbach2011-07-271-2/+0
| | | | | | | | | | Encode the width operand as it encodes in the instruction, which simplifies the disassembler and the encoder, by using the imm1_32 operand def. Add a diagnostic for the context-sensitive constraint that the width must be in the range [1,32-lsb]. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM cleanup of rot_imm encoding.Jim Grosbach2011-07-261-2/+0
| | | | | | | | | Start of cleaning this up a bit. First step is to remove the encoder hook by storing the operand as the bits it'll actually encode to so it can just be directly used. Map it to the assembly source values 8/16/24 when we print it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136152 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of the extraneous GPR operand on so_reg_imm operands, which in turn ↵Owen Anderson2011-07-211-1/+3
| | | | | | necessitates a lot of changes to related bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135722 91177308-0d34-0410-b5e6-96231b3b80d8
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-75/+75
| | | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix ssat and ssat16 encodings for ARM and Thumb. The bit position valueBruno Cardoso Lopes2011-05-311-0/+2
| | | | | | | must be encoded decremented by one. Only add encoding tests for ssat16 because ssat can't be parsed yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed MC encoding for index_align for VLD1/VST1 (single element from one ↵Mon P Wang2011-05-091-0/+3
| | | | | | lane) for size 32 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131085 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the non-MC encoding of pkhbt and pkhtb.Eric Christopher2011-05-071-0/+6
| | | | | | | Patch by Stephen Hines. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131045 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the narrow shift right immediate operands to "shr_imm*" operands. AlsoBill Wendling2011-03-071-3/+5
| | | | | | | | | expand the testing of the narrowing shift right instructions. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
* PR8053: Fix encoding of S bit in some ARM instructions.Bob Wilson2011-03-031-1/+1
| | | | | | Patch by Zonr Chang! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126967 91177308-0d34-0410-b5e6-96231b3b80d8
* Narrow right shifts need to encode their immediates differently from a normalBill Wendling2011-03-011-0/+7
| | | | | | | | | | | shift. 16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0> 32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0> 64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.Jason W Kim2011-02-041-0/+2
| | | | | | | | | | | | | | | | | | | (yes, this is different from R_ARM_CALL) - Adds a new method getARMBranchTargetOpValue() which handles the necessary distinction between the conditional and unconditional br/bl needed for ARM/ELF At least for ARM mode, the needed fixup for conditional versus unconditional br/bl is identical, but the ARM docs and existing ARM tools expect this reloc type... Added a few FIXME's for future naming fixups in ARMInstrInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124895 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for parsing and encoding ARM's official syntax for the BFI ↵Bruno Cardoso Lopes2011-01-181-0/+2
| | | | | | instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123770 91177308-0d34-0410-b5e6-96231b3b80d8
* Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a stepEvan Cheng2011-01-131-1/+1
| | | | | | | | | in the right direction. It eliminated some hacks and will unblock codegen work. But it's far from being done. It doesn't reject illegal expressions, e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123369 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755Jim Grosbach2010-12-141-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121798 91177308-0d34-0410-b5e6-96231b3b80d8
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-141-1/+3
| | | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
* Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering ↵Owen Anderson2010-12-141-0/+2
| | | | | | | | | much later, which makes the entire process cleaner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121735 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r121721, which broke buildbots.Owen Anderson2010-12-131-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121726 91177308-0d34-0410-b5e6-96231b3b80d8
* Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. ↵Owen Anderson2010-12-131-0/+2
| | | | | | | | | Provide correct fixups for Thumb2 ADR, which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121721 91177308-0d34-0410-b5e6-96231b3b80d8
* In Thumb2, direct branches can be encoded as either a "short" conditional ↵Owen Anderson2010-12-131-0/+2
| | | | | | | | | | | branch with a null predicate, or as a "long" direct branch. While the mnemonics are the same, they encode the branch offset differently, and the Darwin assembler appears to prefer the "long" form for direct branches. Thus, in the name of bitwise equivalence, provide encoding and fixup support for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121710 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding of Thumb1 LDRB and STRB.Owen Anderson2010-12-101-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121581 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb unconditional branch binary encoding. rdar://8754994Jim Grosbach2010-12-101-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121496 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb conditional branch binary encodings. rdar://8745367Jim Grosbach2010-12-101-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121493 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of theBill Wendling2010-12-091-5/+1
| | | | | | | | t_addrmode_s# address modes is used for ASM printing, not for encoding. <rdar://problem/8745375> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121417 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the encoder method for t_cbtarget to match.Jim Grosbach2010-12-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121399 91177308-0d34-0410-b5e6-96231b3b80d8
* The BLX instruction is encoded differently than the BL, because why not? InBill Wendling2010-12-091-0/+2
| | | | | | | | | | | particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0' always. Going through the BL fixup encoding was trashing the "bit 0 is '0'" invariant. Attempt to get the encoding at slightly more correct with this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121336 91177308-0d34-0410-b5e6-96231b3b80d8
* Support the "target" encodings for the CB[N]Z instructions.Bill Wendling2010-12-081-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121308 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for loading from a constant pool.Bill Wendling2010-12-081-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121226 91177308-0d34-0410-b5e6-96231b3b80d8
* Binary encoding for ARM tLDRspi and tSTRspi.Jim Grosbach2010-12-071-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121186 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fixup for Thumb1 BL/BLX instructions.Jim Grosbach2010-12-061-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121072 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a post encoder method to the VFP instructions to convert them to the Thumb2Bill Wendling2010-12-011-0/+2
| | | | | | | encoding if we're in that mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120608 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADRJim Grosbach2010-12-011-0/+2
| | | | | | | instruction at MC lowering. Add binary encoding information for the ADR, including fixup data for the label operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120594 91177308-0d34-0410-b5e6-96231b3b80d8
* Add correct encodings for STRD and LDRD, including fixup support. ↵Owen Anderson2010-12-011-0/+2
| | | | | | Additionally, update these to unified syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120589 91177308-0d34-0410-b5e6-96231b3b80d8
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