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* Add support for NEON VLD2-dup instructions.Bob Wilson2010-11-281-7/+96
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120236 91177308-0d34-0410-b5e6-96231b3b80d8
* Add entry in getTargetNodeName() for ARMISD::VBICIMM.Bob Wilson2010-11-281-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120233 91177308-0d34-0410-b5e6-96231b3b80d8
* Recognize sign/zero-extended constant BUILD_VECTORs for VMULL operations.Bob Wilson2010-11-231-13/+109
| | | | | | | We need to check if the individual vector elements are sign/zero-extended values. For now this only handles constants values. Radar 8687140. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120034 91177308-0d34-0410-b5e6-96231b3b80d8
* Renaming ISD::BIT_CONVERT to ISD::BITCAST to better reflect the LLVM IR concept.Wesley Peck2010-11-231-51/+51
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119990 91177308-0d34-0410-b5e6-96231b3b80d8
* These instructions are thumb2 only.Evan Cheng2010-11-191-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119793 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bug in DAGCombiner for ARM that was trying to do a ShiftCombine on ↵Tanya Lattner2010-11-181-1/+2
| | | | | | | | | | illegal types (vector should be split first). Added test case. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119749 91177308-0d34-0410-b5e6-96231b3b80d8
* Move hasFP() and few related hooks to TargetFrameInfo.Anton Korobeynikov2010-11-181-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119740 91177308-0d34-0410-b5e6-96231b3b80d8
* Split up ARM LowerShift function.Bob Wilson2010-11-181-26/+33
| | | | | | | | | | | | | This function was being called from two different places for completely unrelated reasons. During type legalization, it was called to expand 64-bit shift operations. During operation legalization, it was called to handle Neon vector shifts. The vector shift code was not written to check for illegal types, since it was assumed to be only called after type legalization. Fixed this by splitting off the 64-bit shift expansion into a separate function. I don't have a particular testcase for this; I just noticed it by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119738 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an issue where we tried to turn a v2f32 build_vector into a v4i32 build ↵Nate Begeman2010-11-101-2/+2
| | | | | | vector with 2 elts git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118720 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not use MEMBARRIER_MCR for any Thumb code.Bob Wilson2010-11-091-2/+2
| | | | | | | | | It is only supported for ARM code. Normally Thumb2 code would use DMB instead, but depending on how the compiler is invoked (e.g., -mattr=-db) that might be disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that situation. Radar 8644195 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the ARMConstantPoolValue modifier string to an enumeration. This willJim Grosbach2010-11-091-4/+4
| | | | | | help in MC'izing the references that use them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for ARM's specialized vector-compare-against-zero instructions.Owen Anderson2010-11-081-1/+32
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
* Disallow the certain NEON modified-immediate forms when generating vorr or vbic.Owen Anderson2010-11-051-7/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118300 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen and encoding support for the immediate form of vbic.Owen Anderson2010-11-051-1/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118291 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix @llvm.prefetch isel. Selecting between pld / pldw using the first ↵Evan Cheng2010-11-041-10/+11
| | | | | | immediate rw. There is currently no intrinsic that matches to pli. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
* Covert VORRIMM to be produced via early target-specific DAG combining, ↵Owen Anderson2010-11-031-31/+26
| | | | | | | | | rather than legalization. This is both the conceptually correct place for it, as well as allowing it to be more aggressive. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for code generation of the one register with immediate form of vorr.Owen Anderson2010-11-031-0/+29
| | | | | | | | We could be more aggressive about making this work for a larger range of constants, but this seems like a good start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
* Check for extractelement with a variable operand for the element number.Bob Wilson2010-11-031-10/+15
| | | | | | For NEON we had been assuming this was always an immediate constant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118175 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify uses of MVT and EVT. An MVT can be compared directlyDuncan Sands2010-11-031-1/+1
| | | | | | | | with a SimpleValueType, while an EVT supports equality and inequality comparisons with SimpleValueType. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118169 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix preload instruction isel. Only v7 supports pli, and only v7 with mp ↵Evan Cheng2010-11-031-4/+29
| | | | | | extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118160 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.Evan Cheng2010-11-031-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118152 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON does not support truncating vector stores. Radar 8598391.Bob Wilson2010-11-011-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117940 91177308-0d34-0410-b5e6-96231b3b80d8
* Overhaul memory barriers in the ARM backend. Radar 8601999.Bob Wilson2010-10-301-12/+20
| | | | | | | | | | | | | | | | | | | There were a number of issues to fix up here: * The "device" argument of the llvm.memory.barrier intrinsic should be used to distinguish the "Full System" domain from the "Inner Shareable" domain. It has nothing to do with using DMB vs. DSB instructions. * The compiler should never need to emit DSB instructions. Remove the ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB. * Merge the separate DMB/DSB instructions for options only used for the disassembler with the default DMB/DSB instructions. Add the default "full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum. * Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement a data memory barrier using the MCR instruction. * Fix up encodings for these instructions (except MCR). I also updated the tests and added a few new ones to check for DMB options that were not currently being exercised. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117756 91177308-0d34-0410-b5e6-96231b3b80d8
* - Don't schedule nodes with only MVT::Flag and MVT::Other values for latency.Evan Cheng2010-10-291-3/+7
| | | | | | | - Compute CopyToReg use operand latency correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117674 91177308-0d34-0410-b5e6-96231b3b80d8
* Inline asm multiple alternative constraints development phase 2 - improved ↵John Thompson2010-10-291-0/+34
| | | | | | basic logic, added initial platform support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117667 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix compiler warnings about signed/unsigned comparisons.Bob Wilson2010-10-271-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117511 91177308-0d34-0410-b5e6-96231b3b80d8
* SelectionDAG shuffle nodes do not allow operands with different numbers ofBob Wilson2010-10-271-0/+55
| | | | | | | | | | | | | | | | | | | elements than the result vector type. So, when an instruction like: %8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2> is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements. That is: shuffle [a,b], [c,d] is changed to: shuffle [a,b,u,u], [c,d,u,u] That's probably the right thing for x86 but for NEON, we'd much rather have: shuffle [a,b,c,d], undef Teach the DAG combiner how to do that transformation for ARM. Radar 8597007. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117482 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable ARM fastcc.Evan Cheng2010-10-231-5/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117194 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fastcc cc: pass and return VFP / NEON values in registers. Controlled by ↵Evan Cheng2010-10-221-12/+22
| | | | | | -arm-fastcc for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117119 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix crash introduced in 116852. 8573915.Dale Johannesen2010-10-201-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116955 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a pre-dispatch SjLj EH hook on the unwind edge for targets to do anyJim Grosbach2010-10-191-0/+11
| | | | | | | setup they require. Use this for ARM/Darwin to rematerialize the base pointer from the frame pointer when required. rdar://8564268 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116879 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable using vdup for vector constants which are splat ofDale Johannesen2010-10-191-32/+17
| | | | | | | | | integers by default, and remove the controlling flag, now that LICM will hoist such vdup's. 8003375. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116852 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't mark argument value stores as immutable, as otherwise the post-RAJim Grosbach2010-10-151-1/+1
| | | | | | | scheduler may reorder loads from them before the stores and other such badness. PR8347. Patch by David Meyer git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116602 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused ARMISD::AND selection DAG node.Bob Wilson2010-10-151-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116566 91177308-0d34-0410-b5e6-96231b3b80d8
* User proper libcall names & condcodes while compiling for ARM EABI.Anton Korobeynikov2010-09-281-6/+150
| | | | | | Patch by Evzen Muller! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114991 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a command line option "-arm-strict-align" to disallow unaligned memoryBob Wilson2010-09-281-9/+1
| | | | | | | accesses for ARM targets that would otherwise allow it. Radar 8465431. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114941 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable code placement optimization pass for ARM.Evan Cheng2010-09-241-7/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114746 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for ELF PLT references for ARM MC asm printing. Adding aJim Grosbach2010-09-221-4/+16
| | | | | | | | | | new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure there's a more straightforward way to get the printing difference captured. (i.e., x86 uses @PLT, ARM uses (PLT)). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114613 91177308-0d34-0410-b5e6-96231b3b80d8
* Change VDUPLANE DAG combiner to just return the result instead of callingBob Wilson2010-09-221-5/+3
| | | | | | | | | CombineTo to avoid putting the result on the worklist. I don't think it makes much difference for now, but it might help someday as we add more DAG combine optimizations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114595 91177308-0d34-0410-b5e6-96231b3b80d8
* Combine both VMOVDRR(VMOVRRD) and VMOVRRD(VMOVDRR), instead of just doing oneBob Wilson2010-09-221-28/+35
| | | | | | | | | of those. Refactor to share code for handling BUILD_VECTOR(VMOVRRD). I don't have a testcase that exercises this, but it seems like an obvious good thing to do. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114589 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that ↵Owen Anderson2010-09-211-4/+0
| | | | | | | | | this makes irrelevant, but add a new test for the new, improved functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114494 91177308-0d34-0410-b5e6-96231b3b80d8
* convert a couple more places to use the new getStore()Chris Lattner2010-09-211-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114463 91177308-0d34-0410-b5e6-96231b3b80d8
* Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON loadBob Wilson2010-09-211-0/+61
| | | | | | | and store intrinsics are represented with MemIntrinsicSDNodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114454 91177308-0d34-0410-b5e6-96231b3b80d8
* convert the targets off the non-MachinePointerInfo of getLoad.Chris Lattner2010-09-211-31/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
* reimplement memcpy/memmove/memset lowering to use MachinePointerInfoChris Lattner2010-09-211-1/+1
| | | | | | | | instead of srcvalue/offset pairs. This corrects SV info for mem operations whose size is > 32-bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
* Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64Bob Wilson2010-09-171-0/+27
| | | | | | | | | value should be in GPRs when it's going to be used as a scalar, and we use VMOVRRD to make that happen, but if the value is converted back to a vector we need to fold to a simple bit_convert. Radar 8407927. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
* Split out some of the calling convention bits so that they can beEric Christopher2010-09-101-147/+1
| | | | | | | used for fast-isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113652 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach if-converter to be more careful with predicating instructions that wouldEvan Cheng2010-09-101-2/+2
| | | | | | | | | | | | take multiple cycles to decode. For the current if-converter clients (actually only ARM), the instructions that are predicated on false are not nops. They would still take machine cycles to decode. Micro-coded instructions such as LDM / STM can potentially take multiple cycles to decode. If-converter should take treat them as non-micro-coded simple instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113570 91177308-0d34-0410-b5e6-96231b3b80d8
* remove trailing whitespaceJim Grosbach2010-09-081-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113338 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace NEON vabdl, vaba, and vabal intrinsics with combinations of theBob Wilson2010-09-031-17/+0
| | | | | | | | | vabd intrinsic and add and/or zext operations. In the case of vaba, this also avoids the need for a DAG combine pattern to combine vabd with add. Update tests. Auto-upgrade the old intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112941 91177308-0d34-0410-b5e6-96231b3b80d8
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