aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/ARM/ARMMCInstLower.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-071-5/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
* Ignore register mask operands when lowering instructions to MC.Jakob Stoklund Olesen2012-01-181-0/+3
| | | | | | | This is similar to implicit register operands. MC doesn't understand register liveness and call clobbers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148437 91177308-0d34-0410-b5e6-96231b3b80d8
* Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ↵Evan Cheng2011-07-201-1/+1
| | | | | | ARM MC code from target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135636 91177308-0d34-0410-b5e6-96231b3b80d8
* Use TableGen'erated pseudo lowering for ARM.Jim Grosbach2011-07-081-54/+64
| | | | | | | | | | Hook up the TableGen lowering for simple pseudo instructions for ARM and use it for a subset of the many pseudos the backend has as proof of concept. More conversions to come. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134705 91177308-0d34-0410-b5e6-96231b3b80d8
* Add needed braces.Bill Wendling2011-01-261-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124273 91177308-0d34-0410-b5e6-96231b3b80d8
* Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a stepEvan Cheng2011-01-131-8/+18
| | | | | | | | | in the right direction. It eliminated some hacks and will unblock codegen work. But it's far from being done. It doesn't reject illegal expressions, e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123369 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the ARMAsmPrinter class defintiion into a header file.Jim Grosbach2010-12-011-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120551 91177308-0d34-0410-b5e6-96231b3b80d8
* Trailing whitespace.Jim Grosbach2010-11-301-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120497 91177308-0d34-0410-b5e6-96231b3b80d8
* trim #includes.Chris Lattner2010-11-141-5/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119075 91177308-0d34-0410-b5e6-96231b3b80d8
* rename LowerToMCInst -> LowerARMMachineInstrToMCInst.Chris Lattner2010-11-141-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119071 91177308-0d34-0410-b5e6-96231b3b80d8
* even more simplifications. ARM MCInstLowering is now justChris Lattner2010-11-141-12/+11
| | | | | | | | a single function instead of a class. It doesn't need the complexity that X86 does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119070 91177308-0d34-0410-b5e6-96231b3b80d8
* more shrinkificationChris Lattner2010-11-141-5/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119068 91177308-0d34-0410-b5e6-96231b3b80d8
* more simplifications.Chris Lattner2010-11-141-84/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119067 91177308-0d34-0410-b5e6-96231b3b80d8
* simplify and tidy upChris Lattner2010-11-141-27/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119066 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for ELF PLT references for ARM MC asm printing. Adding aJim Grosbach2010-09-221-9/+22
| | | | | | | | | | new VariantKind to the MCSymbolExpr seems like overkill, but I'm not sure there's a more straightforward way to get the printing difference captured. (i.e., x86 uses @PLT, ARM uses (PLT)). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114613 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable a few additional asserts in MC instruction lowering.Jim Grosbach2010-09-221-9/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114601 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a few commented out bitsJim Grosbach2010-09-221-14/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114576 91177308-0d34-0410-b5e6-96231b3b80d8
* handle the upper16/lower16 target operand flags on symbol references for MCJim Grosbach2010-09-171-5/+35
| | | | | | instruction lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114191 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure to promote single precision floats to double before extracting themJim Grosbach2010-09-161-2/+4
| | | | | | from the APFloat. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114096 91177308-0d34-0410-b5e6-96231b3b80d8
* store MC FP immediates as a double instead of as an APFloat, thus avoiding anJim Grosbach2010-09-161-1/+2
| | | | | | unnecessary dtor for MCOperand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114064 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for floating point immediates to MC instruction printing. ARMJim Grosbach2010-09-151-0/+4
| | | | | | | | | | | | | VFP instructions use it for loading some constants, so implement that handling. Not thrilled with adding a member to MCOperand, but not sure there's much of a better option that's not pretty fragile (like putting a double in the union instead and just assuming that's good enough). Suggestions welcome... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113996 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't ignore the CPSR implicit def when lowering a MachineInstruction to an ↵Jim Grosbach2010-09-141-2/+3
| | | | | | MCInst. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113847 91177308-0d34-0410-b5e6-96231b3b80d8
* trailing whitespaceJim Grosbach2010-09-131-14/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113768 91177308-0d34-0410-b5e6-96231b3b80d8
* sink the arm implementations of ASmPrinter and MCInstLowerChris Lattner2010-07-191-0/+162
out of the AsmPrinter directory into libarm. Now the ARM InstPrinters depend jsut on the MC stuff, not on vmcore or codegen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108783 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-11-10 21:09:12 +0000