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* Added ARM::CPSR to represent ARM CPSR status register.Evan Cheng2007-07-051-0/+6
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* Specify S registers as D registers' sub-registers.Evan Cheng2007-04-201-2/+2
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* Change register allocation order to Dale's suggestion.Evan Cheng2007-03-081-14/+18
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* ARM always use register scavenger. No longer reserves R12.Evan Cheng2007-03-071-50/+12
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* Make requiresRegisterScavenging determination on a per MachineFunction basis.Evan Cheng2007-02-281-8/+8
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* Temporary: make R12 available in ARM mode if RegScavenger is being used.Evan Cheng2007-02-281-12/+53
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* Minor tweak. Allocate r0 to r3 in reverse order, r3 is least likely to be ↵Evan Cheng2007-02-271-5/+5
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* Comment.Evan Cheng2007-01-291-1/+1
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* hasFP() is now a virtual method of MRegisterInfo.Evan Cheng2007-01-231-1/+2
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* Clean up ARM PEI code.Evan Cheng2007-01-201-1/+2
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* ARM backend contribution from Apple.Evan Cheng2007-01-191-103/+143
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* initial support for frame pointersRafael Espindola2006-10-261-1/+4
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* fix the names of the 64bit fp registerRafael Espindola2006-10-021-16/+16
| | | | | | | initial support for returning 64bit floating point numbers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30692 91177308-0d34-0410-b5e6-96231b3b80d8
* add floating point registersRafael Espindola2006-09-291-18/+94
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* Constify some methods. Patch provided by Anton Vayvod, thanks!Chris Lattner2006-08-171-2/+2
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* initial implementation of ARMRegisterInfo::eliminateFrameIndexRafael Espindola2006-06-181-1/+7
| | | | | | | fixes test/Regression/CodeGen/ARM/ret_arg5.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28854 91177308-0d34-0410-b5e6-96231b3b80d8
* added a skeleton of the ARM backendRafael Espindola2006-05-141-0/+56
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28301 91177308-0d34-0410-b5e6-96231b3b80d8
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