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* Make processor FUs unique for given itinerary. This extends the limit of 32Anton Korobeynikov2010-04-181-15/+1
| | | | | | | FU per CPU arch to 32 per intinerary allowing precise modelling of quite complex pipelines in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101754 91177308-0d34-0410-b5e6-96231b3b80d8
* Split A8/A9 itins - they already were too big.Anton Korobeynikov2010-04-071-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100672 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix itins for VABAAnton Korobeynikov2010-04-071-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100657 91177308-0d34-0410-b5e6-96231b3b80d8
* VHADD differs from VHSUB at least on A9 - the former reads both operands in ↵Anton Korobeynikov2010-04-071-0/+2
| | | | | | the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100652 91177308-0d34-0410-b5e6-96231b3b80d8
* Define new itin classes for ARM <-> VFP reg moves to distinguish from NEON ↵Anton Korobeynikov2010-04-071-0/+4
| | | | | | ops. Define proper scheduling itinerary for them on A9. A8 TRM does not specify latency for them at all :( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100650 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new itin classes for FP16 <-> FP32 conversions and make uise of them for A9.Anton Korobeynikov2010-04-071-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100647 91177308-0d34-0410-b5e6-96231b3b80d8
* Make use of new reserved/required scheduling stuff: introduce VFP and NEON ↵Anton Korobeynikov2010-04-071-0/+2
| | | | | | locks to model domain cross stalls precisly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100646 91177308-0d34-0410-b5e6-96231b3b80d8
* Finish scheduling itineraries for NEON.David Goodwin2009-09-251-4/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82788 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the end-of-itinerary mark explicit. Some cleanup.David Goodwin2009-09-241-84/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82709 91177308-0d34-0410-b5e6-96231b3b80d8
* Checkpoint NEON scheduling itineraries.David Goodwin2009-09-231-1/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82657 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Cortex-A8 VFP model.David Goodwin2009-09-211-10/+68
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82483 91177308-0d34-0410-b5e6-96231b3b80d8
* Update Cortex-A8 instruction itineraries for integer instructions.David Goodwin2009-08-191-17/+91
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79436 91177308-0d34-0410-b5e6-96231b3b80d8
* Turn on if-conversion for thumb2.Evan Cheng2009-08-151-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79084 91177308-0d34-0410-b5e6-96231b3b80d8
* Finalize itineraries for cortex-a8 integer multiplyDavid Goodwin2009-08-131-2/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78908 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow a zero cycle stage to reserve/require a FU without advancing the cycle ↵David Goodwin2009-08-111-5/+10
| | | | | | counter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78736 91177308-0d34-0410-b5e6-96231b3b80d8
* Checkpoint scheduling itinerary changes.David Goodwin2009-08-101-6/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78564 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fake v7 itineraries for now.Evan Cheng2009-07-211-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76612 91177308-0d34-0410-b5e6-96231b3b80d8
* Latency information for ARM v6. It's rough and not yet hooked up. Right now ↵Evan Cheng2009-06-191-0/+35
we are only using branch latency to determine if-conversion limits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73747 91177308-0d34-0410-b5e6-96231b3b80d8
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