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* Emit a '!' if this is a "writeback" register or memory address.Bill Wendling2010-11-101-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118662 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename a parameter to avoid confusion with a local variableMatt Beaumont-Gay2010-11-101-3/+3
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* Emit the warning about the register list not being in ascending order only once.Bill Wendling2010-11-091-5/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8
* s/std::vector/SmallVector/Bill Wendling2010-11-091-12/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete the allocated vector.Bill Wendling2010-11-091-0/+4
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* Two types of instructions have register lists:Bill Wendling2010-11-091-56/+32
| | | | | | | | | | | | * LDM, et al, uses a bit mask to indicate the register list. * VLDM, et al, uses a base register plus number. The LDM instructions may be non-contiguous, but the VLDM ones must be contiguous. Those are semantic checks that should be done later in the compiler. Also postpone the creation of the bit mask until it's needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118640 91177308-0d34-0410-b5e6-96231b3b80d8
* The "addRegListOperands()" function returns the start register and the totalBill Wendling2010-11-081-15/+21
| | | | | | | number of registers in the list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118456 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert.Bill Wendling2010-11-081-1/+1
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* In this context, a reglist is a reg.Bill Wendling2010-11-071-1/+1
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* Add support for parsing register lists. We can't use a bitfield to keep track ofBill Wendling2010-11-061-22/+64
| | | | | | | | | | | | the registers, because the register numbers may be much greater than the number of bits available in the machine's register. I extracted the register list verification code out of the actual parsing of the registers. This made checking for errors much easier. It also limits the number of warnings that would be emitted for cascading infractions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118363 91177308-0d34-0410-b5e6-96231b3b80d8
* Return the base register of a register list for the "getReg()" method. This isBill Wendling2010-11-061-3/+8
| | | | | | | | to satisfy the ClassifyOperand method of the Asm matcher without having to add a RegList type to every back-end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118360 91177308-0d34-0410-b5e6-96231b3b80d8
* General cleanup:Bill Wendling2010-11-061-36/+21
| | | | | | | | - Make ARMOperand a class so that some things are internal to the class. - Reformatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118357 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a RegList (register list) object to ARMOperand. It will be used soon to holdBill Wendling2010-11-061-1/+38
| | | | | | | | (surprise!) a list of registers. Register lists are consecutive, so we only need to record the start register plus the number of registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118351 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix grammar.Bill Wendling2010-11-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118341 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix grammar.Bill Wendling2010-11-061-3/+3
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* MatchRegisterName() returns 0 if it can't match the register.Bill Wendling2010-11-061-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118339 91177308-0d34-0410-b5e6-96231b3b80d8
* Use TryParseRegister() instead of MatchRegisterName(). The former returns -1Bill Wendling2010-11-061-5/+2
| | | | | | | while the latter doesn't. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118338 91177308-0d34-0410-b5e6-96231b3b80d8
* Hook up the '.code {16|32}' directive to the streamer.Jim Grosbach2010-11-051-2/+5
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* Hook up the '.thumb_func' directive to the streamer.Jim Grosbach2010-11-051-3/+5
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* Fix past-o.Jim Grosbach2010-11-051-1/+1
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* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-031-3/+13
| | | | | | | | | | | | | vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FIXME.Jim Grosbach2010-11-011-0/+1
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* Mark ARM subtarget features that are available for the assembler.Jim Grosbach2010-11-011-1/+5
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* trailing whitespaceJim Grosbach2010-11-011-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117927 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up.Jim Grosbach2010-10-301-1/+1
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* simplify this code.Chris Lattner2010-10-301-8/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117771 91177308-0d34-0410-b5e6-96231b3b80d8
* split MaybeParseRegister into its two logical uses, eliminating malloc+free ↵Chris Lattner2010-10-301-35/+38
| | | | | | traffic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117769 91177308-0d34-0410-b5e6-96231b3b80d8
* Some instructions end with an "ls" prefix, but it doesn't indicate that they areBill Wendling2010-10-291-3/+9
| | | | | | | conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
* add FIXMEJim Grosbach2010-10-291-0/+5
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* Handle ARM addrmode5 instructions with an offset.Jim Grosbach2010-10-291-9/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117672 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 117660. Apparently it's not as trivial as that...Jim Grosbach2010-10-291-2/+2
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* ARM addrmode5 instructions have neither writeback nor post-indexed modes.Jim Grosbach2010-10-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117660 91177308-0d34-0410-b5e6-96231b3b80d8
* Trailing whitespace.Jim Grosbach2010-10-291-30/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117651 91177308-0d34-0410-b5e6-96231b3b80d8
* ARMAsmParser: Plug a memory leak.Benjamin Kramer2010-10-291-2/+3
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* Add an unreachable to silence warning - the switch is actuallyEric Christopher2010-10-291-0/+2
| | | | | | | fully enumerated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117647 91177308-0d34-0410-b5e6-96231b3b80d8
* add simple support for addrmode5 operands, allowingChris Lattner2010-10-291-10/+25
| | | | | | | | vldr.64 to work. I have no idea if this is fully right, but it is in the right direction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117626 91177308-0d34-0410-b5e6-96231b3b80d8
* give better error diagnostics, for example:Chris Lattner2010-10-281-5/+20
| | | | | | | | | | | | | | | | t.s:1:14: error: invalid operand for instruction vldr.64 d17, [r0] ^ instead of: t.s:1:1: error: unrecognized instruction vldr.64 d17, [r0] ^ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117611 91177308-0d34-0410-b5e6-96231b3b80d8
* move a method out of line.Chris Lattner2010-10-281-13/+20
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* remove the rest of hte owningptr's, no functionality change.Chris Lattner2010-10-281-57/+59
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* rearrange ParseRegisterList.Chris Lattner2010-10-281-16/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117560 91177308-0d34-0410-b5e6-96231b3b80d8
* refactor some code to simplify it, eliminating some owningptr's.Chris Lattner2010-10-281-65/+60
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* Remove remaining uses of ATTRIBUTE_UNUSED on variables, and delete threeChandler Carruth2010-10-201-2/+0
| | | | | | | #includes in the process. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116919 91177308-0d34-0410-b5e6-96231b3b80d8
* implement rdar://8456378 and PR7557 - support for the fstsw,Chris Lattner2010-09-291-2/+2
| | | | | | | | an instruction that requires a WHOLE NEW wonderful kind of alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115015 91177308-0d34-0410-b5e6-96231b3b80d8
* change the protocol TargetAsmPArser::MatchInstruction method to take anChris Lattner2010-09-291-4/+6
| | | | | | | | MCStreamer to emit into instead of an MCInst to fill in. This allows the matcher extra flexibility and is more convenient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115014 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally."Michael J. Spencer2010-09-131-6/+0
| | | | | | | | | | This reverts commit r113632 Conflicts: cmake/modules/AddLLVM.cmake git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113819 91177308-0d34-0410-b5e6-96231b3b80d8
* fix the asmparser so that the target is responsible for skipping toChris Lattner2010-09-111-4/+11
| | | | | | | | | | | | | | | the end of the line on a parser error, allowing skipping to happen for syntactic errors but not for semantic errors. Before we would miss emitting a diagnostic about the second line, because we skipped it due to the semantic error on the first line: foo %eax bar %al This fixes rdar://8414033 - llvm-mc ignores lines after an invalid instruction mnemonic errors git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113688 91177308-0d34-0410-b5e6-96231b3b80d8
* CMake: Get rid of LLVMLibDeps.cmake and export the libraries normally.Michael J. Spencer2010-09-101-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113632 91177308-0d34-0410-b5e6-96231b3b80d8
* change the MC "ParseInstruction" interface to make it the Chris Lattner2010-09-081-0/+5
| | | | | | | | implementation's job to check for and lex the EndOfStatement marker. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113347 91177308-0d34-0410-b5e6-96231b3b80d8
* in the case where an instruction only has one implementationChris Lattner2010-09-061-1/+2
| | | | | | | | | | | | | | | | | | | | | | of a mneumonic, report operand errors with better location info. For example, we now report: t.s:6:14: error: invalid operand for instruction cwtl $1 ^ but we fail for common cases like: t.s:11:4: error: invalid operand for instruction addl $1, $1 ^ because we don't know if this is supposed to be the reg/imm or imm/reg form. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113178 91177308-0d34-0410-b5e6-96231b3b80d8
* change MatchInstructionImpl to return an enum instead of bool.Chris Lattner2010-09-061-1/+1
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