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* More not-crashing NEON disassembly updates for the vld refactoring.Owen Anderson2011-10-311-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143351 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r143202, with a manual decoding hook for SWP. This change ↵Owen Anderson2011-10-281-0/+24
| | | | | | inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143208 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some NEON stores to the VLD decoding hook that were accidentally omitted ↵Owen Anderson2011-10-271-0/+4
| | | | | | previously. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143162 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VLD1 with writeback.Jim Grosbach2011-10-251-4/+8
| | | | | | | Four entry register lists. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-241-4/+8
| | | | | | | Three entry register list variation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-241-12/+51
| | | | | | | | | | Split am6offset into fixed and register offset variants so the instruction encodings are explicit rather than relying an a magic reg0 marker. Needed to being able to parse these. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142853 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a NEON disassembly case that was broken in the recent refactorings. As ↵Owen Anderson2011-10-241-6/+0
| | | | | | more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142817 91177308-0d34-0410-b5e6-96231b3b80d8
* Move various generated tables into read-only memory, fixing up const ↵Benjamin Kramer2011-10-221-1/+1
| | | | | | correctness along the way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142726 91177308-0d34-0410-b5e6-96231b3b80d8
* Assembly parsing for 4-register sequential variant of VLD2.Jim Grosbach2011-10-211-18/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-211-6/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-211-24/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-211-16/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM VLD parsing and encoding.Jim Grosbach2011-10-211-8/+0
| | | | | | | | | | | | | | | Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up. Trailing whitespace.Jim Grosbach2011-10-201-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142591 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed set, but unused variables.Chad Rosier2011-10-171-10/+0
| | | | | | | Patch by Joe Abbey <jabbey@arxan.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142223 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a non-firing assert. Change:Richard Trieu2011-10-141-1/+1
| | | | | | | | | assert("bad SymbolicOp.VariantKind"); To: assert(0 && "bad SymbolicOp.VariantKind"); git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142000 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix undefined shift. Patch by Ahmed Charles.Eli Friedman2011-10-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141914 91177308-0d34-0410-b5e6-96231b3b80d8
* SETEND is not allowed in an IT block.Owen Anderson2011-10-131-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141874 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM addrmode5 represents the 'U' bit of the encoding backwards.Jim Grosbach2011-10-121-14/+17
| | | | | | | The disassembler needs to use the AM5 factory methods instead of just building up the immediate directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141819 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDC/STC.Jim Grosbach2011-10-121-24/+50
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
* addrmode2 is gone from these, so no need for the reg0 operand.Jim Grosbach2011-10-121-24/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141794 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the check for nested IT instructions in the disassembler. We need to ↵Owen Anderson2011-10-061-3/+6
| | | | | | perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141339 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding back support for printing operands symbolically to ARM's new disassemblerKevin Enderby2011-10-041-3/+211
| | | | | | | | | | | | | | | | | | | | using llvm's public 'C' disassembler API now including annotations. Hooked this up to Darwin's otool(1) so it can again print things like branch targets for example this: blx _puts instead of this: blx #-36 and includes support for annotations for branches to symbol stubs like: bl 0x40 @ symbol stub for: _puts and annotations for pc relative loads like this: ldr r3, #8 @ literal pool for: Hello, world! Also again can print the expression encoded in the Mach-O relocation entries for things like this: movt r0, :upper16:((_foo-_bar)+1234) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141129 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.Jim Grosbach2011-09-301-27/+0
| | | | | | | | | | | | | Encode the immediate into its 8-bit form as part of isel rather than later, which simplifies things for mapping the encoding bits, allows the removal of the custom disassembler decoding hook, makes the operand printer trivial, and prepares things more cleanly for handling these in the asm parser. rdar://10211428 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140834 91177308-0d34-0410-b5e6-96231b3b80d8
* ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.Owen Anderson2011-09-261-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140560 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid ↵Owen Anderson2011-09-231-1/+1
| | | | | | testcases updated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140415 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r140412. This affects more instructions than intended.Owen Anderson2011-09-231-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140413 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 register-shifted-register loads cannot target the PC or the SP.Owen Anderson2011-09-231-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140412 91177308-0d34-0410-b5e6-96231b3b80d8
* tMOVSr is not allowed in an IT block either.Owen Anderson2011-09-191-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140104 91177308-0d34-0410-b5e6-96231b3b80d8
* CPS instructions are UNPREDICTABLE inside IT blocks.Owen Anderson2011-09-191-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140102 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 TBB and TBH instructions are only allowed at the end of IT blocks, ↵Owen Anderson2011-09-191-0/+2
| | | | | | not in the middle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140079 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for TBB/TBH.Jim Grosbach2011-09-191-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle STRT (and friends) like LDRT (and friends) for decoding purposes. ↵Owen Anderson2011-09-191-0/+3
| | | | | | Port over additional encoding tests to decoding tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140032 91177308-0d34-0410-b5e6-96231b3b80d8
* Bitfield mask instructions are unpredictable if the encoded LSB is higher ↵Owen Anderson2011-09-161-1/+4
| | | | | | than the encoded MSB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139972 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bitfield decoding based on Eli's feedback.Owen Anderson2011-09-161-4/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139969 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 pre-indexed loads/stores use the restricted GPR set for Rt.Owen Anderson2011-09-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139965 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32).Owen Anderson2011-09-161-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139964 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix disassembly of Thumb2 LDRSH with a #-0 offset.Owen Anderson2011-09-161-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139943 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't attach annotations to MCInst's. Instead, have the disassembler ↵Owen Anderson2011-09-151-4/+8
| | | | | | return, and the printer accept, an annotation string which can be passed through if the client cares about annotations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139876 91177308-0d34-0410-b5e6-96231b3b80d8
* Nested IT blocks are UNPREDICTABLE. Mark them as such when disassembling them.Owen Anderson2011-09-141-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139736 91177308-0d34-0410-b5e6-96231b3b80d8
* Port more encoding tests to decoding tests, and correct an improper Thumb2 ↵Owen Anderson2011-09-121-0/+32
| | | | | | pre-indexed load decoding this uncovered. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139522 91177308-0d34-0410-b5e6-96231b3b80d8
* LDM writeback is not allowed if Rn is in the target register list.Owen Anderson2011-09-091-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.Owen Anderson2011-09-091-0/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb unconditional branches are allowed in IT blocks, and therefore should ↵Owen Anderson2011-09-091-4/+14
| | | | | | have a predicate operand, unlike conditional branches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.Jim Grosbach2011-09-091-0/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
* All conditional branches are disallowed in IT blocks, not just CBZ/CBNZ.Owen Anderson2011-09-081-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139329 91177308-0d34-0410-b5e6-96231b3b80d8
* Soft fail CBZ/CBNZ in the disassembler if they appear inside an IT block.Owen Anderson2011-09-081-12/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139328 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 assembly parsing and encoding for LDRD(immediate).Jim Grosbach2011-09-081-0/+76
| | | | | | Refactor operand handling for STRD as well. Tests for that forthcoming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the "common" set of instructions shared between ARM and Thumb2 modes. ↵Owen Anderson2011-09-081-18/+0
| | | | | | This is no longer needed now that Thumb2 has its own copy of the STC/LDC instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139268 91177308-0d34-0410-b5e6-96231b3b80d8
* Create Thumb2 versions of STC/LDC, and reenable the relevant tests.Owen Anderson2011-09-071-0/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139256 91177308-0d34-0410-b5e6-96231b3b80d8
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