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* Constants with multiple encodings (ARM):Johnny Chen2011-04-051-2/+3
| | | | | | | | | | | An alternative syntax is available for a modified immediate constant that permits the programmer to specify the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where: <byte> is the numeric value of abcdefgh, in the range 0-255 <rot> is twice the numeric value of rotation, an even number in the range 0-30. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128897 91177308-0d34-0410-b5e6-96231b3b80d8
* - Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHTBruno Cardoso Lopes2011-04-042-5/+50
| | | | | | | | | | also fix the encoding of the later. - Add a new encoding bit to describe the index mode used in AM3. - Teach printAddrMode3Operand to check by the addressing mode which index mode to print. - Testcases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
* Apply again changes to support ARM memory asm parsing. I removedBruno Cardoso Lopes2011-03-312-8/+50
| | | | | | | | | | | | | | all LDR/STR changes and left them to a future patch. Passing all checks now. - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and fix the encoding wherever is possible. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r128632 again, until I figure out what break the testsBruno Cardoso Lopes2011-03-312-50/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r128585 without generating a lib depedency cycle. An updated log:Bruno Cardoso Lopes2011-03-312-8/+50
| | | | | | | | | | | | | - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and {STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible. - Move all instructions which use am2offset without a pattern to use addrmode2. - Add a new encoding bit to describe the index mode used and teach printAddrMode2Operand to check by the addressing mode which index mode to print. - Testcases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"Matt Beaumont-Gay2011-03-312-57/+10
| | | | | | This revision introduced a dependency cycle, as nlewycky mentioned by email. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
* - Implement asm parsing support for LDRT, LDRBT, STRT, STRBT andBruno Cardoso Lopes2011-03-302-10/+57
| | | | | | | | | | | | | | | {STR,LDC}{2}_PRE. - Fixed the encoding in some places. - Some of those instructions were using am2offset and now use addrmode2. Codegen isn't affected, instructions which use SelectAddrMode2Offset were not touched. - Teach printAddrMode2Operand to check by the addressing mode which index mode to print. - This is a work in progress, more work to come. The idea is to change places which use am2offset to use addrmode2 instead, as to unify assembly parser. - Add testcases for assembly parser git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
* Add asm parsing support w/ testcases for strex/ldrex family of instructionsBruno Cardoso Lopes2011-03-242-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
* We need to pass the TargetMachine object to the InstPrinter if we are printingBill Wendling2011-03-211-2/+5
| | | | | | | | | | the alias of an InstAlias instead of the thing being aliased. Because we need to know the features that are valid for an InstAlias. This is part of a work-in-progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127986 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some dead patterns.Jim Grosbach2011-03-142-12/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127601 91177308-0d34-0410-b5e6-96231b3b80d8
* Preliminary support for ARM frame save directives emission via MI flags.Anton Korobeynikov2011-03-052-0/+4
| | | | | | | This is just very first approximation how the stuff should be done (e.g. ARM-only for now). More to follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127101 91177308-0d34-0410-b5e6-96231b3b80d8
* Add assembly parsing support for "msr" and also fix its encoding. Also addBruno Cardoso Lopes2011-02-181-1/+8
| | | | | | | | testcases for the disassembler to make sure it still works for "msr". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-142-20/+14
| | | | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-081-3/+0
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125127 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for printing out floating point values from the ARM assemblyBill Wendling2011-01-261-2/+27
| | | | | | | | parser. The parser will always give us a binary representation of the floating point number. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124318 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 124230. It was causing test failures.Bill Wendling2011-01-251-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124233 91177308-0d34-0410-b5e6-96231b3b80d8
* The floating point value is encoded in its binary form as an Imm. Convert itBill Wendling2011-01-251-2/+4
| | | | | | | appropriately so that it prints out the decimal representation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124230 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to the ARM MC infrastructure to support mcr and friends. This ↵Owen Anderson2011-01-132-0/+12
| | | | | | | | | | | | | | | requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes <rdar://problem/8857858>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123404 91177308-0d34-0410-b5e6-96231b3b80d8
* The tLDR et al instructions were emitting either a reg/reg or reg/immBill Wendling2010-12-142-33/+37
| | | | | | | | | | | | | | | | | instruction based on the t_addrmode_s# mode and what it returned. There is some obvious badness to this. In particular, it's hard to do MC-encoding when the instruction may change out from underneath you after the t_addrmode_s# variable is finally resolved. The solution is to revert a long-ago change that merged the reg/reg and reg/imm versions. There is the addition of several new addressing modes. They no longer have extraneous operands associated with them. I.e., if it's reg/reg we don't have to have a dummy zero immediate tacked on to the SDNode. There are some obvious cleanups here, which will happen shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121747 91177308-0d34-0410-b5e6-96231b3b80d8
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-071-0/+3
| | | | | | gazillion places that need to know about it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121082 91177308-0d34-0410-b5e6-96231b3b80d8
* When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's theJim Grosbach2010-12-031-0/+4
| | | | | | 32-bit wide version by adding the .w suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120838 91177308-0d34-0410-b5e6-96231b3b80d8
* Pseudo-ize Thumb2 jump tables with explicit MC lowering to the rawJim Grosbach2010-11-292-12/+0
| | | | | | instructions. This simplifies instruction printing and disassembly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120333 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename t2 TBB and TBH instructions to reference that they encode the jump tableJim Grosbach2010-11-291-1/+1
| | | | | | data. Next up, pseudo-izing them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120320 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM Pseudo-ize tBR_JTr.Jim Grosbach2010-11-291-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120310 91177308-0d34-0410-b5e6-96231b3b80d8
* Encode the multi-load/store instructions with their respective modes ('ia',Bill Wendling2010-11-161-36/+24
| | | | | | | | | | 'db', 'ib', 'da') instead of having that mode as a separate field in the instruction. It's more convenient for the asm parser and much more readable for humans. <rdar://problem/8654088> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119310 91177308-0d34-0410-b5e6-96231b3b80d8
* stub out a powerpc MCInstPrinter implementation.Chris Lattner2010-11-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119059 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor cleanups:Bill Wendling2010-11-131-6/+8
| | | | | | | | - Get the opcode once. - Add a ParserMatchClass to reglist. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118997 91177308-0d34-0410-b5e6-96231b3b80d8
* For pre-v6t2 targets, only select MOVi32imm if the immediate can be handled ↵Evan Cheng2010-11-122-9/+0
| | | | | | with movi + orr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118945 91177308-0d34-0410-b5e6-96231b3b80d8
* The MC code couldn't handle ARM LDR instructions with negative offsets:Bill Wendling2010-11-031-1/+1
| | | | | | | | | | | | | vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused function.Jim Grosbach2010-11-032-9/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118141 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the no longer used 'Modifier' optional operand to the ARMJim Grosbach2010-11-032-17/+8
| | | | | | printOperand() asm printer helper functions. rdar://8425198 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118140 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused function.Jim Grosbach2010-11-032-12/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118139 91177308-0d34-0410-b5e6-96231b3b80d8
* Break ARM addrmode4 (load/store multiple base address) into its constituentJim Grosbach2010-11-032-14/+5
| | | | | | | parts. Represent the operation mode as an optional operand instead. rdar://8614429 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118137 91177308-0d34-0410-b5e6-96231b3b80d8
* hook up getOpcodeName for ARM so that "llc -show-mc-inst" includesChris Lattner2010-10-282-0/+9
| | | | | | | | | | | | | | | | | the opcode string in the inst dump, e.g.: vmov r2, r3, d17 @ encoding: [0x31,0x2b,0x53,0xec] @ <MCInst #989 VMOVRRD @ <MCOperand Reg:68> @ <MCOperand Reg:69> @ <MCOperand Reg:19> @ <MCOperand Imm:14> @ <MCOperand Reg:0>> The "VMOVRRD" is new. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117609 91177308-0d34-0410-b5e6-96231b3b80d8
* PLD, PLDW, PLI encodings, plus refactor their use of addrmode2.Jim Grosbach2010-10-281-2/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117571 91177308-0d34-0410-b5e6-96231b3b80d8
* LDRi12 machine instructions handle negative offset operands normally (simpleJim Grosbach2010-10-271-2/+5
| | | | | | integer values), not with the addrmode2 encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117429 91177308-0d34-0410-b5e6-96231b3b80d8
* First part of refactoring ARM addrmode2 (load/store) instructions to be moreJim Grosbach2010-10-261-0/+5
| | | | | | | | explicit about the operands. Split out the different variants into separate instructions. This gives us the ability to, among other things, assign different scheduling itineraries to the variants. rdar://8477752. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117409 91177308-0d34-0410-b5e6-96231b3b80d8
* imm12 operands aren't Thumb2 only, so rename the printer helper function.Jim Grosbach2010-10-252-5/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117291 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor the ARM 'setend' instruction pattern. Use a single instruction patternJim Grosbach2010-10-132-0/+10
| | | | | | | and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8
* Kill of the vestiges of the 'call' Modifier (no longer needed for PLT).Jim Grosbach2010-10-061-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115845 91177308-0d34-0410-b5e6-96231b3b80d8
* Now that VDUPfqf and VDUPfdfare properly pseudos, kill the no-longer-neededJim Grosbach2010-10-061-30/+1
| | | | | | | | "lane" operand modifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115843 91177308-0d34-0410-b5e6-96231b3b80d8
* PrintSpecial() can go away now.Jim Grosbach2010-10-011-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115376 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the AsmPrinter directory to InstPrinter for those targets that haveJim Grosbach2010-10-014-0/+871
been MC-ized for assembly printing. MSP430 is mostly so, but still has the asm printer and lowering code in the printer subdir for the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115360 91177308-0d34-0410-b5e6-96231b3b80d8
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