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* Update aosp/master LLVM for rebase to r235153Pirama Arumuga Nainar2015-05-1813-61/+63
| | | | | Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7 (cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
* Update aosp/master llvm for rebase to r233350Pirama Arumuga Nainar2015-04-0910-195/+131
| | | | Change-Id: I07d935f8793ee8ec6b7da003f6483046594bca49
* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-2310-55/+187
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-0221-400/+522
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for rebase to r212749.Stephen Hines2014-07-219-245/+62
| | | | | | | Includes a cherry-pick of: r212948 - fixes a small issue with atomic calls Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-2915-115/+348
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-2421-806/+1709
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* am b7485134: am 449fc261: Merge "llvm: convert makefiles to support multilib ↵Colin Cross2014-02-181-2/+0
|\ | | | | | | | | | | | | build" * commit 'b7485134a2cbecc47904988b4cfde24019ac4fa1': llvm: convert makefiles to support multilib build
| * llvm: convert makefiles to support multilib buildColin Cross2014-02-061-2/+0
| | | | | | | | | | | | | | | | Convert makefiles to allow for building two architectures at the same time. This will also cause make checkbuild to build the target libraries for all supported architectures. Change-Id: Ia5e6fe5b1186a67753faafd3532ed4cb280a8b10
* | Merge remote-tracking branch 'upstream/release_34' into merge-20140211Stephen Hines2014-02-1110-183/+669
|\ \ | |/ |/| | | | | | | | | | | Conflicts: lib/Linker/LinkModules.cpp lib/Support/Unix/Signals.inc Change-Id: Ia54f291fa5dc828052d2412736e8495c1282aa64
| * ARM: Add subtarget feature for CRCBernard Ogden2013-10-291-2/+2
| | | | | | | | | | | | | | | | Adds a subtarget feature for the CRC instructions (optional in v8-A) to the ARM (32-bit) backend. Differential Revision: http://llvm-reviews.chandlerc.com/D2036 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193599 91177308-0d34-0410-b5e6-96231b3b80d8
| * Return early from getUnconditionalBranchTargetOpValue if the branch target isLang Hames2013-10-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | an MCExpr, in order to avoid writing an encoded zero value in the immediate field. When getUnconditionalBranchTargetOpValue is called with an MCExpr target, we don't know what the final immediate field value should be. We shouldn't explicitly set the immediate field to an encoded zero value as zero is encoded with a non-zero bit pattern. This leads to bits being set that pollute the final immediate value. The nature of the encoding is such that the polluted bits only affect very large immediate values, explaining why this hasn't caused problems earlier. Fixes <rdar://problem/15155975>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193535 91177308-0d34-0410-b5e6-96231b3b80d8
| * [arm] Implement eabi_attribute, cpu, and fpu directives.Logan Chien2013-10-281-0/+333
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit allows the ARM integrated assembler to parse and assemble the code with .eabi_attribute, .cpu, and .fpu directives. To implement the feature, this commit moves the code from AttrEmitter to ARMTargetStreamers, and several new test cases related to cortex-m4, cortex-r5, and cortex-a15 are added. Besides, this commit also change the Subtarget->isFPOnlySP() to Subtarget->hasD16() to match the usage of .fpu directive. This commit changes the test cases: * Several .eabi_attribute directives in 2010-09-29-mc-asm-header-test.ll are removed because the .fpu directive already cover the functionality. * In the Cortex-A15 test case, the value for Tag_Advanced_SIMD_arch has be changed from 1 to 2, which is more precise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193524 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add a MCAsmInfoELF class and factor some code into it.Rafael Espindola2013-10-162-3/+2
| | | | | | | | | | | | We had a MCAsmInfoCOFF, but no common class for all the ELF MCAsmInfos before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192760 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add subtarget feature support for Cortex-A53Bernard Ogden2013-10-141-2/+7
| | | | | | | | | | | | | | Some previous implicit defaults have changed, for example FP and NEON are now on by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192590 91177308-0d34-0410-b5e6-96231b3b80d8
| * Flip the ownership of MCStreamer and MCTargetStreamer.Benjamin Kramer2013-10-091-1/+1
| | | | | | | | | | | | | | MCStreamer now owns the target streamer. This prevents leaking the target streamer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192303 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add a MCTargetStreamer interface.Rafael Espindola2013-10-083-44/+167
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
| * [ARM] Improve build attributes emission.Amara Emerson2013-10-071-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192111 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove some really nasty uses of hasRawTextSupport.Rafael Espindola2013-10-053-35/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When MC was first added, targets could use hasRawTextSupport to keep features working before they were added to the MC interface. The design goal of MC is to provide an uniform api for printing assembly and object files. Short of relaxations and other corner cases, a object file is just another representation of the assembly. It was never the intention that targets would keep doing things like if (hasRawTextSupport()) Set flags in one way. else Set flags in another way. When they do that they create two code paths and the object file is no longer just another representation of the assembly. This also then requires testing with llc -filetype=obj, which is extremelly brittle. This patch removes some of these hacks by replacing them with smaller ones. The ARM flag setting is trivial, so I just moved it to the constructor. For Mips, the patch adds two temporary hack directives that allow the assembly to represent the same things as the object file was already able to. The hope is that the mips developers will replace the hack directives with the same ones that gas uses and drop the -print-hack-directives flag. I will also try to implement a target streamer interface, so that we can move this out of the common code. In summary, for any new work, two rules of the thumb are * Don't use "llc -filetype=obj" in tests. * Don't add calls to hasRawTextSupport. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192035 91177308-0d34-0410-b5e6-96231b3b80d8
| * [ARM] Warn on deprecated IT blocks in v8 AArch32 assembly.Amara Emerson2013-10-031-0/+11
| | | | | | | | | | | | | | Patch by Artyom Skrobov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191885 91177308-0d34-0410-b5e6-96231b3b80d8
| * [ARM] Use the load-acquire/store-release instructions optimally in AArch32.Amara Emerson2013-09-261-1/+1
| | | | | | | | | | | | | | Patch by Artyom Skrobov. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191428 91177308-0d34-0410-b5e6-96231b3b80d8
| * Added support for generate DWARF .debug_aranges sections automatically.Richard Mitton2013-09-191-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191052 91177308-0d34-0410-b5e6-96231b3b80d8
| * [ARM] Fix the deprecation of MCR encodings that map to CP15{ISB,DSB,DMB}.Joey Gouly2013-09-171-8/+25
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190862 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
| * Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-092-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We used to generate the compact unwind encoding from the machine instructions. However, this had the problem that if the user used `-save-temps' or compiled their hand-written `.s' file (with CFI directives), we wouldn't generate the compact unwind encoding. Move the algorithm that generates the compact unwind encoding into the MCAsmBackend. This way we can generate the encoding whether the code is from a `.ll' or `.s' file. <rdar://problem/13623355> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
| * [ARMv8] Implement the new DMB/DSB operands.Joey Gouly2013-09-051-9/+9
| | | | | | | | | | | | | | | | | | This removes the custom ISD Node: MEMBARRIER and replaces it with an intrinsic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190055 91177308-0d34-0410-b5e6-96231b3b80d8
| * Move everything depending on Object/MachOFormat.h over to Support/MachO.h.Charles Davis2013-09-012-81/+80
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189728 91177308-0d34-0410-b5e6-96231b3b80d8
| * Clean up some usage of Triple. The base class has methods for determining ↵Cameron Esfahani2013-08-291-2/+1
| | | | | | | | | | | | if the target is iOS and Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189604 91177308-0d34-0410-b5e6-96231b3b80d8
| * Revert "Fix the build broken by r189315." and "Move everything depending on ↵Charles Davis2013-08-272-79/+81
| | | | | | | | | | | | | | | | | | Object/MachOFormat.h over to Support/MachO.h." This reverts commits r189319 and r189315. r189315 broke some tests on what I believe are big-endian platforms. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189321 91177308-0d34-0410-b5e6-96231b3b80d8
| * Move everything depending on Object/MachOFormat.h over to Support/MachO.h.Charles Davis2013-08-272-81/+79
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189315 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for Thumb2 literal loads with negative zero offsetMihai Popa2013-08-161-2/+4
| | | | | | | | | | | | | | | | | | | | Thumb2 literal loads use an offset encoding which allows for negative zero. This fixes parsing and encoding so that #-0 is correctly processed. The parser represents #-0 as INT32_MIN. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188549 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix signed overflow in when computing encodings for ADR instructionsMihai Popa2013-08-131-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188268 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix assembling of Thumb2 branch instructions.Mihai Popa2013-08-091-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The long encoding for Thumb2 unconditional branches is broken. Additionally, there is no range checking for target operands; as such for instructions originating in assembly code, only short Thumb encodings are generated, regardless of the bitsize needed for the offset. Adding range checking is non trivial due to the representation of Thumb branch instructions. There is no true difference between conditional and unconditional branches in terms of operands and syntax - even unconditional branches have a predicate which is expected to match that of the IT block they are in. Yet, the encodings and the permitted size of the offset differ. Due to this, for any mnemonic there are really 4 encodings to choose for. The problem cannot be handled in the parser alone or by manipulating td files. Because the parser builds first a set of match candidates and then checks them one by one, whatever tablegen-only solution might be found will ultimately be dependent of the parser's evaluation order. What's worse is that due to the fact that all branches have the same syntax and the same kinds of operands, that order is governed by the lexicographical ordering of the names of operand classes... To circumvent all this, any necessary disambiguation is added to the instruction validation pass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188067 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge commit '10251753b6897adcd22cc981c0cc42f348c109de' into merge-20130807Stephen Hines2013-08-074-52/+77
|\ \ | |/ | | | | | | | | | | | | Conflicts: lib/Archive/ArchiveReader.cpp lib/Support/Unix/PathV2.inc Change-Id: I29d8c1e321a4a380b6013f00bac6a8e4b593cc4e
| * This adds range checking for "ldr Rn, [pc, #imm]" Thumb Mihai Popa2013-07-221-1/+1
| | | | | | | | | | | | | | | | | | | | instructions. With this patch: 1. ldr.n is recognized as mnemonic for the short encoding 2. ldr.w is recognized as menmonic for the long encoding 3. ldr will map to either short or long encodings depending on the size of the offset git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186831 91177308-0d34-0410-b5e6-96231b3b80d8
| * [ARMv8] Add support for the NEON instructions vmaxnm/vminnm.Joey Gouly2013-07-171-0/+13
| | | | | | | | | | | | | | | | This adds a new class for non-predicable NEON instructions and a new DecoderNamespace for v8 NEON instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186504 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove address spaces from MC.Rafael Espindola2013-07-021-11/+10
| | | | | | | | | | | | | | | | This is dead code since PIC16 was removed in 2010. The result was an odd mix, where some parts would carefully pass it along and others would assert it was zero (most of the object streamer for example). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185436 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix ARM EHABI compact model 1 and 2 without handlerdata.Logan Chien2013-07-021-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to ARM EHABI section 9.2, if the __aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is used, then the handler data must be emitted after the unwind opcodes. The handler data consists of several words, and should be terminated by zero. In case that the .handlerdata directive is not specified by the programmer, we should emit zero to terminate the handler data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185422 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add a subtarget feature 'v8' to the ARM backend.Joey Gouly2013-06-261-1/+4
| | | | | | | | | | | | | | This allows for targeting the ARMv8 AArch32 variant. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184967 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARM: fix literal load with positive offset encodingAmaury de la Vieuville2013-06-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | When using a positive offset, literal loads where encoded as if it was negative, because: - The sign bit was not assigned to an operand - The addrmode_imm12 operand was not encoding the sign bit correctly This patch also makes the assembler look at the .w/.n specifier for loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184182 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use pointers to the MCAsmInfo and MCRegInfo.Bill Wendling2013-06-182-35/+35
| | | | | | | | | | | | | | | | | | | | Someone may want to do something crazy, like replace these objects if they change or something. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184175 91177308-0d34-0410-b5e6-96231b3b80d8
* | Update LLVM for merge to r183849.Stephen Hines2013-06-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | s/LLVM_HOSTTRIPLE/LLVM_HOST_TRIPLE Add #include<ctype.h> to LinkModules.cpp for isdigit(). Add missing libLLVMObject to llc dependencies. Android.mk updates: Remove Linker.cpp Remove JITDwarfEmitter.cpp Remove MipsDirectObjLower.cpp Add MCExternalSymbolizer.cpp Add MCRelocationInfo.cpp Add MCSymbolizer.cpp Add ARMMachORelocationInfo.cpp Add Mips16HardFloat.cpp Add MipsOptimizeMathLibCalls.cpp Add X86ELFRelocationInfo.cpp Add X86MachORelocationInfo.cpp Change-Id: I3f3dbc2b62e89ef9e303f5456c6a99f0937f6981
* | Merge commit '100fbdd06be7590b23c4707a98cd605bdb519498' into merge_20130612Stephen Hines2013-06-1211-210/+342
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| * Rework r183728, suppress assert(0) for now. Its behavior depends on ↵NAKAMURA Takumi2013-06-111-1/+4
| | | | | | | | | | | | | | | | assertions on win32 hosts. FIXME: Introduce yet another checker but assert(0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183736 91177308-0d34-0410-b5e6-96231b3b80d8
| * Tweak a couple of tests on win32 hosts with +Asserts.NAKAMURA Takumi2013-06-111-1/+1
| | | | | | | | | | | | | | | | | | - Don't use assert(0), or tests may pass or fail according to assertions. - For now, The tests are marked as XFAIL for win32 hosts. FIXME: Could we avoid XFAIL to specify triple in the RUN lines? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183728 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARMAsmBackend.cpp: Use Triple::isOSBinFormatCOFF() instead of isOSWindows().NAKAMURA Takumi2013-06-111-1/+1
| | | | | | | | | | | | FYI, isOSBinFormatCOFF() is as same as isOSWindows(), on trunk. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183727 91177308-0d34-0410-b5e6-96231b3b80d8
| * Whitespace.NAKAMURA Takumi2013-06-111-5/+5
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183726 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARM: diagnose ARM/Thumb assembly switches on CPUs only supporting one.Tim Northover2013-06-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | Some ARM CPUs only support ARM mode (ancient v4 ones, for example) and some only support Thumb mode (M-class ones currently). This makes sure such CPUs default to the correct mode and makes the AsmParser diagnose an attempt to switch modes incorrectly. rdar://14024354 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183710 91177308-0d34-0410-b5e6-96231b3b80d8
| * Silencing an MSVC warning about comparing signed and unsigned values.Aaron Ballman2013-06-101-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183682 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARM: ISB cannot be passed the same options as DMBAmaury de la Vieuville2013-06-101-0/+43
| | | | | | | | | | | | ISB should only accepts full system sync, other options are reserved git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183656 91177308-0d34-0410-b5e6-96231b3b80d8
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