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* Renamed MCInstFragment to MCRelaxableFragment and added some comments.Eli Bendersky2013-01-081-2/+2
| | | | | | | | No change in functionality. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171822 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Copy-paste error.Jim Grosbach2013-01-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171790 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Fix a few copy-paste errors.Jim Grosbach2013-01-072-3/+3
| | | | | | s/X86/ARM/ git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171789 91177308-0d34-0410-b5e6-96231b3b80d8
* Change SMRange to be half-open (exclusive end) instead of closed (inclusive)Jordan Rose2013-01-071-82/+90
| | | | | | | | | | This is necessary not only for representing empty ranges, but for handling multibyte characters in the input. (If the end pointer in a range refers to a multibyte character, should it point to the beginning or the end of the character in a char array?) Some of the code in the asm parsers was already assuming this anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171765 91177308-0d34-0410-b5e6-96231b3b80d8
* Add LICENSE.TXT covering contributions made by ARM.Tim Northover2013-01-071-0/+47
| | | | | | | | | | Absent a Contributor's License Agreement (CLA) with an LLVM legal entity and as reviewed and agreed with Chris Lattner, add a patent license covering future contributions from ARM until there is a CLA. This is to make explicit ARM's grant of patent rights to recipients of LLVM containing ARM-contributed material. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171721 91177308-0d34-0410-b5e6-96231b3b80d8
* Move TargetTransformInfo to live under the Analysis library. This noChandler Carruth2013-01-071-1/+1
| | | | | | | longer would violate any dependency layering and it is in fact an analysis. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171686 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch TargetTransformInfo from an immutable analysis pass that requiresChandler Carruth2013-01-077-64/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | a TargetMachine to construct (and thus isn't always available), to an analysis group that supports layered implementations much like AliasAnalysis does. This is a pretty massive change, with a few parts that I was unable to easily separate (sorry), so I'll walk through it. The first step of this conversion was to make TargetTransformInfo an analysis group, and to sink the nonce implementations in ScalarTargetTransformInfo and VectorTargetTranformInfo into a NoTargetTransformInfo pass. This allows other passes to add a hard requirement on TTI, and assume they will always get at least on implementation. The TargetTransformInfo analysis group leverages the delegation chaining trick that AliasAnalysis uses, where the base class for the analysis group delegates to the previous analysis *pass*, allowing all but tho NoFoo analysis passes to only implement the parts of the interfaces they support. It also introduces a new trick where each pass in the group retains a pointer to the top-most pass that has been initialized. This allows passes to implement one API in terms of another API and benefit when some other pass above them in the stack has more precise results for the second API. The second step of this conversion is to create a pass that implements the TargetTransformInfo analysis using the target-independent abstractions in the code generator. This replaces the ScalarTargetTransformImpl and VectorTargetTransformImpl classes in lib/Target with a single pass in lib/CodeGen called BasicTargetTransformInfo. This class actually provides most of the TTI functionality, basing it upon the TargetLowering abstraction and other information in the target independent code generator. The third step of the conversion adds support to all TargetMachines to register custom analysis passes. This allows building those passes with access to TargetLowering or other target-specific classes, and it also allows each target to customize the set of analysis passes desired in the pass manager. The baseline LLVMTargetMachine implements this interface to add the BasicTTI pass to the pass manager, and all of the tools that want to support target-aware TTI passes call this routine on whatever target machine they end up with to add the appropriate passes. The fourth step of the conversion created target-specific TTI analysis passes for the X86 and ARM backends. These passes contain the custom logic that was previously in their extensions of the ScalarTargetTransformInfo and VectorTargetTransformInfo interfaces. I separated them into their own file, as now all of the interface bits are private and they just expose a function to create the pass itself. Then I extended these target machines to set up a custom set of analysis passes, first adding BasicTTI as a fallback, and then adding their customized TTI implementations. The fourth step required logic that was shared between the target independent layer and the specific targets to move to a different interface, as they no longer derive from each other. As a consequence, a helper functions were added to TargetLowering representing the common logic needed both in the target implementation and the codegen implementation of the TTI pass. While technically this is the only change that could have been committed separately, it would have been a nightmare to extract. The final step of the conversion was just to delete all the old boilerplate. This got rid of the ScalarTargetTransformInfo and VectorTargetTransformInfo classes, all of the support in all of the targets for producing instances of them, and all of the support in the tools for manually constructing a pass based around them. Now that TTI is a relatively normal analysis group, two things become straightforward. First, we can sink it into lib/Analysis which is a more natural layer for it to live. Second, clients of this interface can depend on it *always* being available which will simplify their code and behavior. These (and other) simplifications will follow in subsequent commits, this one is clearly big enough. Finally, I'm very aware that much of the comments and documentation needs to be updated. As soon as I had this working, and plausibly well commented, I wanted to get it committed and in front of the build bots. I'll be doing a few passes over documentation later if it sticks. Commits to update DragonEgg and Clang will be made presently. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171681 91177308-0d34-0410-b5e6-96231b3b80d8
* Move all of the header files which are involved in modelling the LLVM IRChandler Carruth2013-01-0222-63/+63
| | | | | | | | | | | | | | | | | | | | | into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
* Resort the #include lines in include/... and lib/... with theChandler Carruth2013-01-022-2/+2
| | | | | | | | | | utils/sort_includes.py script. Most of these are updating the new R600 target and fixing up a few regressions that have creeped in since the last time I sorted the includes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171362 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the Function::getRetAttributes method in favor of using the ↵Bill Wendling2012-12-301-2/+1
| | | | | | AttributeSet accessor method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171256 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the Function::getFnAttributes method in favor of using the AttributeSetBill Wendling2012-12-305-12/+19
| | | | | | | | | | directly. This is in preparation for removing the use of the 'Attribute' class as a collection of attributes. That will shift to the AttributeSet class instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171253 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a std::string rather than a dynamically allocated char* buffer.Benjamin Kramer2012-12-242-21/+6
| | | | | | | | | | | | | This affords us to use std::string's allocation routines and use the destructor for the memory management. Switching to that also means that we can use operator==(const std::string&, const char *) to perform the string comparison rather than resorting to libc functionality (i.e. strcmp). Patch by Saleem Abdulrasool! Differential Revision: http://llvm-reviews.chandlerc.com/D230 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171042 91177308-0d34-0410-b5e6-96231b3b80d8
* Cleanup compiler warnings on discarding type qualifiers in casts. Switch to ↵Benjamin Kramer2012-12-212-6/+10
| | | | | | | | | | C++ style casts. Patch by Saleem Abdulrasool! Differential Revision: http://llvm-reviews.chandlerc.com/D204 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170917 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove duplicate includes.Roman Divacky2012-12-213-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170902 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM cortex-r5 subtarget.Quentin Colombet2012-12-212-1/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170840 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an MF argument to MI::copyImplicitOps().Jakob Stoklund Olesen2012-12-203-4/+4
| | | | | | | | | This function is often used to decorate dangling instructions, so a context reference is required to allocate memory for the operands. Also add a corresponding MachineInstrBuilder method. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170797 91177308-0d34-0410-b5e6-96231b3b80d8
* MachineInstrBuilderize ARM.Jakob Stoklund Olesen2012-12-201-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170795 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Adding support for llvm.arm.neon.vaddl[su].* and"Bob Wilson2012-12-203-66/+4
| | | | | | | This reverts r170694. The operations can be represented in IR without adding any new intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170765 91177308-0d34-0410-b5e6-96231b3b80d8
* On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,Evan Cheng2012-12-204-77/+103
| | | | | | | | | | are more expensive than the non-flag setting variant. Teach thumb2 size reduction pass to avoid generating them unless we are optimizing for size. rdar://12892707 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170728 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove MCTargetAsmLexer and its derived classes now that edis,Roman Divacky2012-12-203-138/+0
| | | | | | | its only user, is gone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170699 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding support for llvm.arm.neon.vaddl[su].* andRenato Golin2012-12-203-4/+66
| | | | | | | | | | llvm.arm.neon.vsub[su].* intrinsics. Patch by Pete Couperus <pjcoup@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170694 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Add MCInstrDesc::mayAffectControlFlow() method.Jim Grosbach2012-12-192-2/+2
| | | | | | | | | MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the explicit MachineInstrBuilder(MI) constructor.Jakob Stoklund Olesen2012-12-194-11/+9
| | | | | | | | | | | | | Use the version that also takes an MF reference instead. It would technically be possible to extract an MF reference from the MI as MI->getParent()->getParent(), but that would not work for MIs that are not inserted into any basic block. Given the reasonably small number of places this constructor was used at all, I preferred the compile time check to a run time assertion. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170588 91177308-0d34-0410-b5e6-96231b3b80d8
* LLVM sdisel normalize bit extraction of the form:Evan Cheng2012-12-191-2/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ((x & 0xff00) >> 8) << 2 to (x >> 6) & 0x3fc This is general goodness since it folds a left shift into the mask. However, the trailing zeros in the mask prevents the ARM backend from using the bit extraction instructions. And worse since the mask materialization may require an addition instruction. This comes up fairly frequently when the result of the bit twiddling is used as memory address. e.g. = ptr[(x & 0xFF0000) >> 16] We want to generate: ubfx r3, r1, #16, #8 ldr.w r3, [r0, r3, lsl #2] vs. mov.w r9, #1020 and.w r2, r9, r1, lsr #14 ldr r2, [r0, r2] Add a late ARM specific isel optimization to ARMDAGToDAGISel::PreprocessISelDAG(). It folds the left shift to the 'base + offset' address computation; change the mask to one which doesn't have trailing zeros and enable the use of ubfx. Note the optimization has to be done late since it's target specific and we don't want to change the DAG normalization. It's also fairly restrictive as shifter operands are not always free. It's only done for lsh 1 / 2. It's known to be free on some cpus and they are most common for address computation. This is a slight win for blowfish, rijndael, etc. rdar://12870177 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170581 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-193-18/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-192-3/+3
| | | | | | | of EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170532 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the 'Attributes' class to 'Attribute'. It's going to represent a ↵Bill Wendling2012-12-196-13/+13
| | | | | | single attribute in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170502 91177308-0d34-0410-b5e6-96231b3b80d8
* Disable ARM partial flag dependency optimization at -OzQuentin Colombet2012-12-181-2/+10
| | | | | | | | | To not over constrain the scheduler for ARM in thumb mode, some optimizations for code size reduction, specific to ARM thumb, are blocked when they add a dependency (like write after read dependency). Disables this check when code size is the priority, i.e., code is compiled with -Oz. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170462 91177308-0d34-0410-b5e6-96231b3b80d8
* Repair bundles that were broken by removing and reinserting the firstJakob Stoklund Olesen2012-12-181-1/+8
| | | | | | | | | | instruction. This isn't strictly necessary at the moment because Thumb2SizeReduction also copies all MI flags from the old instruction to the new. However, a future patch will make that kind of direct flag tampering illegal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170395 91177308-0d34-0410-b5e6-96231b3b80d8
* Extract a method, no functional change intended.Jakob Stoklund Olesen2012-12-181-31/+35
| | | | | | Sadly, this costs us a perfectly good opportunity to use 'goto'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170385 91177308-0d34-0410-b5e6-96231b3b80d8
* [arm fast-isel] Minor cleanup. No functional change intended.Chad Rosier2012-12-171-10/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170379 91177308-0d34-0410-b5e6-96231b3b80d8
* [arm fast-isel] Fast-isel only handles simple VTs, so make sure the necessaryChad Rosier2012-12-171-10/+20
| | | | | | checks are in place. Some minor cleanup as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170360 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert/correct some FastISel changes in r170104 (EVT->MVT forPatrik Hagglund2012-12-171-11/+19
| | | | | | | | | | TargetLowering::getRegClassFor). Some isSimple() guards were missing, or getSimpleVT() were hoisted too far, resulting in asserts on valid LLVM assembly input. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170336 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure the alternate PC+imm syntax of LDR instruction with a smallKevin Enderby2012-12-141-1/+6
| | | | | | | | | immediate generates the narrow version. Needed when doing round-trip assemble/disassemble testing using the alternate syntax that specifies 'pc' directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170255 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-133-43/+37
| | | | | | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. This is the second attempt. In the first attempt (r169837), a few getSimpleVT() were hoisted too far, detected by bootstrap failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170104 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM NONE and PREL31 relocation types.Logan Chien2012-12-121-1/+8
| | | | | | | | | | Add R_ARM_NONE and R_ARM_PREL31 relocation types to MCExpr. Both of them will be used while generating .ARM.extab and .ARM.exidx sections. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169965 91177308-0d34-0410-b5e6-96231b3b80d8
* Sorry about the churn. One more change to getOptimalMemOpType() hook. Did IEvan Cheng2012-12-122-3/+3
| | | | | | | | | | | | | mention the inline memcpy / memset expansion code is a mess? This patch split the ZeroOrLdSrc argument into two: IsMemset and ZeroMemset. The first indicates whether it is expanding a memset or a memcpy / memmove. The later is whether the memset is a memset of zero. It's totally possible (likely even) that targets may want to do different things for memcpy and memset of zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169959 91177308-0d34-0410-b5e6-96231b3b80d8
* - Rename isLegalMemOpType to isSafeMemOpType. "Legal" is a very overloade term.Evan Cheng2012-12-122-14/+3
| | | | | | | | | | Also added more comments to explain why it is generally ok to return true. - Rename getOptimalMemOpType argument IsZeroVal to ZeroOrLdSrc. It's meant to be true for loaded source (memcpy) or zero constants (memset). The poor name choice is probably some kind of legacy issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169954 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid using lossy load / stores for memcpy / memset expansion. e.g.Evan Cheng2012-12-122-0/+11
| | | | | | | f64 load / store on non-SSE2 x86 targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169944 91177308-0d34-0410-b5e6-96231b3b80d8
* Trim unneeded header #include.Jim Grosbach2012-12-111-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169933 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Remove old testing option.Jim Grosbach2012-12-111-5/+1
| | | | | | | Pre-regalloc frame allocation and referencing has been on by default for ages. No need for the testing option that disables it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169931 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: Remove old testing options.Jim Grosbach2012-12-111-13/+0
| | | | | | Base pointer referencing has been enabled for ages. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169930 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace TargetLowering::isIntImmLegal() withEvan Cheng2012-12-113-22/+46
| | | | | | | | | | ScalarTargetTransformInfo::getIntImmCost() instead. "Legal" is a poorly defined term for something like integer immediate materialization. It is always possible to materialize an integer immediate. Whether to use it for memcpy expansion is more a "cost" conceern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169929 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert EVT->MVT changes, r169836-169851, due to buildbot failures.Patrik Hagglund2012-12-113-40/+46
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169854 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::findRepresentativeClass to take an MVT, insteadPatrik Hagglund2012-12-112-3/+3
| | | | | | | of EVT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169845 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.Patrik Hagglund2012-12-113-43/+37
| | | | | | | | | | Accordingly, add helper funtions getSimpleValueType (in parallel to getValueType) in SDValue, SDNode, and TargetLowering. This is the first, in a series of patches. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169837 91177308-0d34-0410-b5e6-96231b3b80d8
* Stylistic tweak.Evan Cheng2012-12-111-9/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169811 91177308-0d34-0410-b5e6-96231b3b80d8
* Fall back to the selection dag isel to select tail calls.Chad Rosier2012-12-111-0/+3
| | | | | | | | | | | | | | | | | | | This shouldn't affect codegen for -O0 compiles as tail call markers are not emitted in unoptimized compiles. Testing with the external/internal nightly test suite reveals no change in compile time performance. Testing with -O1, -O2 and -O3 with fast-isel enabled did not cause any compile-time or execution-time failures. All tests were performed on my x86 machine. I'll monitor our arm testers to ensure no regressions occur there. In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue and objc_retainAutoreleaseReturnValue as tail calls unconditionally. While it's theoretically true that this is just an optimization, it's an optimization that we very much want to happen even at -O0, or else ARC applications become substantially harder to debug. Part of rdar://12553082 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169796 91177308-0d34-0410-b5e6-96231b3b80d8
* Some enhancements for memcpy / memset inline expansion.Evan Cheng2012-12-103-17/+60
| | | | | | | | | | | | | | | | | | | | | | 1. Teach it to use overlapping unaligned load / store to copy / set the trailing bytes. e.g. On 86, use two pairs of movups / movaps for 17 - 31 byte copies. 2. Use f64 for memcpy / memset on targets where i64 is not legal but f64 is. e.g. x86 and ARM. 3. When memcpy from a constant string, do *not* replace the load with a constant if it's not possible to materialize an integer immediate with a single instruction (required a new target hook: TLI.isIntImmLegal()). 4. Use unaligned load / stores more aggressively if target hooks indicates they are "fast". 5. Update ARM target hooks to use unaligned load / stores. e.g. vld1.8 / vst1.8. Also increase the threshold to something reasonable (8 for memset, 4 pairs for memcpy). This significantly improves Dhrystone, up to 50% on ARM iOS devices. rdar://12760078 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169791 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify code. Sort includes. No functionality change.Benjamin Kramer2012-12-081-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169676 91177308-0d34-0410-b5e6-96231b3b80d8
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