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* Avoid some 's' 16-bit instruction which partially update CPSRBob Wilson2011-04-194-86/+182
| | | | | | | (and add false dependency) when it isn't dependent on last CPSR defining instruction. rdar://8928208 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129773 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid write-after-write issue hazards for Cortex-A9.Bob Wilson2011-04-192-0/+25
| | | | | | | | | | | Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
* Some single-precision VFP instructions can execute in either the VPF or NeonBob Wilson2011-04-191-0/+24
| | | | | | pipelines, at least on Cortex-A9. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129771 91177308-0d34-0410-b5e6-96231b3b80d8
* Improvements for the Cortex-A9 scheduling itineraries.Bob Wilson2011-04-191-12/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129770 91177308-0d34-0410-b5e6-96231b3b80d8
* Change A9 scheduling itineraries VLD* / VST* entries default to "aligned". ThatEvan Cheng2011-04-192-172/+373
| | | | | | | | | | is, it assumes addresses are 64-bit aligned (which should be the more common case). If the alignment is found not to be aligned, then getOperandLatency() would adjust the operand latency computation by one to compensate for it. rdar://9294833 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129742 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not lose mem_operands while lowering VLD / VST intrinsics.Evan Cheng2011-04-192-4/+37
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129738 91177308-0d34-0410-b5e6-96231b3b80d8
* Trim a few unneeded includes.Jim Grosbach2011-04-183-31/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129723 91177308-0d34-0410-b5e6-96231b3b80d8
* Small fix to the ARM AsmParser to ensure that aSean Callanan2011-04-181-0/+1
| | | | | | | superclass variable is instantiated properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129713 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct result when a branch condition is live across a blockStuart Hastings2011-04-161-4/+10
| | | | | | | boundary. <rdar://problem/8933028> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129634 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 BFC was insufficiently encoded.Johnny Chen2011-04-152-1/+3
| | | | | | | rdar://problem/9292717 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129619 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.315 VLD3 (single 3-element structure to all lanes)Johnny Chen2011-04-151-0/+6
| | | | | | | | | The a bit must be encoded as 0. rdar://problem/9292625 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129618 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generateCameron Zwarich2011-04-151-1/+9
| | | | | | a case involving EOR, so I only added a test for ORR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129610 91177308-0d34-0410-b5e6-96231b3b80d8
* The AND instruction leaves the V flag unmodified, so it falls victim to the sameCameron Zwarich2011-04-151-7/+6
| | | | | | problem as all of the other instructions we fold with CMPs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129602 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing register forms of instructions to the ARM CMP-folding code. ThisCameron Zwarich2011-04-151-0/+12
| | | | | | fixes <rdar://problem/9287901>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129599 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-1510-14/+14
| | | | | | | | Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix another fcopysign lowering bug. If src is f64 and destination is f32, don'tEvan Cheng2011-04-151-1/+4
| | | | | | | forget to right shift the source by 32 first. rdar://9287902 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129556 91177308-0d34-0410-b5e6-96231b3b80d8
* For t2BFI, both Inst{26} and Inst{5} "should" be 0.Johnny Chen2011-04-151-0/+4
| | | | | | | Ref: I.1 Instruction encoding diagrams and pseudocode git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129552 91177308-0d34-0410-b5e6-96231b3b80d8
* The ARM disassembler did not handle the alignment correctly for VLD*DUP* ↵Johnny Chen2011-04-151-0/+27
| | | | | | | | | instructions (single element or n-element structure to all lanes). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129550 91177308-0d34-0410-b5e6-96231b3b80d8
* Follow up on r127913. Fix Thumb revsh isel. rdar://9286766Evan Cheng2011-04-141-1/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129548 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity checkings for Thumb2 Load/Store Register Exclusive family of ↵Johnny Chen2011-04-141-4/+41
| | | | | | operations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129531 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb disassembler did not handle tBRIND (indirect branch) properly.Johnny Chen2011-04-131-6/+10
| | | | | | | rdar://problem/9280370 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129480 91177308-0d34-0410-b5e6-96231b3b80d8
* Check for unallocated instruction encodings when disassembling Thumb Branch ↵Johnny Chen2011-04-131-5/+11
| | | | | | | | | instructions (tBcc and t2Bcc). rdar://problem/9280470 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129471 91177308-0d34-0410-b5e6-96231b3b80d8
* The LDR*T/STR*T (unpriviledged load/store) operations don't take SP or PC as Rt.Johnny Chen2011-04-132-8/+16
| | | | | | | rdar://problem/9279440 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129469 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo in an ARM-specific DAG combine. This fixes <rdar://problem/9278274>.Cameron Zwarich2011-04-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129468 91177308-0d34-0410-b5e6-96231b3b80d8
* Check the corner cases for t2LDRSHi12 correctly and mark invalid encodings ↵Johnny Chen2011-04-131-1/+33
| | | | | | | | | as such. rdar://problem/9276651 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129462 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug where for t2MOVCCi disassembly, the TIED_TO register operand was ↵Johnny Chen2011-04-131-3/+11
| | | | | | | | | not properly handled. rdar://problem/9276427 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129456 91177308-0d34-0410-b5e6-96231b3b80d8
* Forgot to add this change for ↵Johnny Chen2011-04-131-4/+4
| | | | | | http://llvm.org/viewvc/llvm-project?view=rev&revision=129387. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129451 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a typo.Cameron Zwarich2011-04-132-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129429 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity check for Ld/St Dual forms of Thumb2 instructions.Johnny Chen2011-04-121-0/+29
| | | | | | | rdar://problem/9273947 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129411 91177308-0d34-0410-b5e6-96231b3b80d8
* Add @earlyclobber constraints to the writeback register of all ARM store ↵Jakob Stoklund Olesen2011-04-122-12/+24
| | | | | | | | | | instructions. The ARMARM specifies these instructions as unpredictable when storing the writeback register. This shouldn't affect code generation much since storing a pointer to itself is quite rare. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129409 91177308-0d34-0410-b5e6-96231b3b80d8
* The Thumb2 RFE instructions need to have their second halfword fully specified.Johnny Chen2011-04-122-6/+11
| | | | | | | | | | | In addition, the base register is not rGPR, but GPR with th exception that: if n == 15 then UNPREDICTABLE rdar://problem/9273836 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129391 91177308-0d34-0410-b5e6-96231b3b80d8
* Add bad register checks for Thumb2 Ld/St instructions.Johnny Chen2011-04-121-0/+45
| | | | | | | rdar://problem/9269047 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129387 91177308-0d34-0410-b5e6-96231b3b80d8
* The Thumb2 Ld, St, and Preload instructions with the i12 forms should have ↵Johnny Chen2011-04-122-0/+5
| | | | | | | | | | | its Inst{23} be specified as '1' (add = TRUE). Also add a utility function for Thumb2. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129377 91177308-0d34-0410-b5e6-96231b3b80d8
* Print out a debug message when the reglist fails the sanity check for Thumb ↵Johnny Chen2011-04-122-0/+29
| | | | | | Ld/St Multiple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129365 91177308-0d34-0410-b5e6-96231b3b80d8
* Split a store of a VMOVDRR into two integer stores to avoid mixing NEON and ARMCameron Zwarich2011-04-121-2/+22
| | | | | | | stores of arguments in the same cache line. This fixes the second half of <rdar://problem/8674845>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129345 91177308-0d34-0410-b5e6-96231b3b80d8
* A8.6.16 BJohnny Chen2011-04-121-0/+5
| | | | | | | | | | Encoding T1 (tBcc) if cond == '1110' then UNDEFINED; rdar://problem/9268681 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129325 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb disassembler was erroneously rejecting "blx sp" instruction.Johnny Chen2011-04-112-2/+14
| | | | | | | rdar://problem/9267838 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the bug where the immediate shift amount for Thumb logical shift ↵Johnny Chen2011-04-111-6/+17
| | | | | | | | | instructions are incorrectly disassembled. rdar://problem/9266265 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129298 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix another using-CPSR-twice bug in my ADCS/SBCS cleanups, and make proper ↵Owen Anderson2011-04-111-2/+5
| | | | | | use of the Commutable bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129294 91177308-0d34-0410-b5e6-96231b3b80d8
* Trivial comment fix.Johnny Chen2011-04-112-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129288 91177308-0d34-0410-b5e6-96231b3b80d8
* Check invalid register encodings for LdFrm/StFrm ARM instructions and flag ↵Johnny Chen2011-04-111-0/+68
| | | | | | | | | them as invalid instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129286 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding support for printing operands symbolically to llvm's public 'C'Kevin Enderby2011-04-114-6/+139
| | | | | | | | | | | | | | disassembler API. Hooked this up to the ARM target so such tools as Darwin's otool(1) can now print things like branch targets for example this: blx _puts instead of this: blx #-36 And even print the expression encoded in the Mach-O relocation entried for things like this: movt r0, :upper16:((_foo-_bar)+1234) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129284 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't include Operator.h from InstrTypes.h.Jay Foad2011-04-111-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129271 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an apparent typo that made GCC complainMatt Beaumont-Gay2011-04-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129160 91177308-0d34-0410-b5e6-96231b3b80d8
* Change -arm-trap-func= into a non-arm specific option. Now Intrinsic::trap ↵Evan Cheng2011-04-081-23/+1
| | | | | | is lowered into a call to the specified trap function at sdisel time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129152 91177308-0d34-0410-b5e6-96231b3b80d8
* Check opcoe (dmb, dsb) instead of bitfields matching.Johnny Chen2011-04-081-12/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129148 91177308-0d34-0410-b5e6-96231b3b80d8
* Hanlde the checking of bad regs for SMMLAR properly, instead of asserting.Johnny Chen2011-04-081-9/+10
| | | | | | | | PR9650 rdar://problem/9257565 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129147 91177308-0d34-0410-b5e6-96231b3b80d8
* Sanity check the option operand for DMB/DSB.Johnny Chen2011-04-082-8/+29
| | | | | | | | PR9648 rdar://problem/9257634 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129146 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark hasExtraDefRegAllocReq=1 on LDRD.Jim Grosbach2011-04-081-1/+5
| | | | | | | | | | The previous cleanup of LDRD got overzealous and removed it, causing post-RA scheduling to get overzealous in breaking antidependencies and invalidate these instructions. Hilarity and invalid assembly ensued. rdar://9244161 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129144 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sanity checking for bad register specifier(s) for the DPFrm instructions.Johnny Chen2011-04-081-0/+30
| | | | | | | Add more test cases to exercise the logical branches related to the above change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129117 91177308-0d34-0410-b5e6-96231b3b80d8
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