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* Another fix to prevent debug info from affecting codegen. rdar://7797940Jim Grosbach2010-06-041-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105470 91177308-0d34-0410-b5e6-96231b3b80d8
* more dbg_value adjustments so debug info doesn't affect codegenJim Grosbach2010-06-041-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105454 91177308-0d34-0410-b5e6-96231b3b80d8
* fix typoJim Grosbach2010-06-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105441 91177308-0d34-0410-b5e6-96231b3b80d8
* For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs andBob Wilson2010-06-043-31/+75
| | | | | | | | | | | | VECTOR_SHUFFLEs to REG_SEQUENCE instructions. The standard ISD::BUILD_VECTOR node corresponds closely to REG_SEQUENCE but I couldn't use it here because its operands do not get legalized. That is pretty awful, but I guess it makes sense for other targets. Instead, I have added an ARM-specific version of BUILD_VECTOR that will have its operands properly legalized. This fixes the rest of Radar 7872877. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105439 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the ARM load-store optimizer to deal with dbg_value instructions.Jim Grosbach2010-06-031-4/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105427 91177308-0d34-0410-b5e6-96231b3b80d8
* Early implementation of tail call for ARM.Dale Johannesen2010-06-035-6/+371
| | | | | | | | | | | A temporary flag -arm-tail-calls defaults to off, so there is no functional change by default. Intrepid users may try this; simple cases work but there are bugs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105413 91177308-0d34-0410-b5e6-96231b3b80d8
* Slightly change the meaning of the reMaterialize target hook when the originalJakob Stoklund Olesen2010-06-024-13/+5
| | | | | | | | | | | | | | | | | | | | | | | instruction defines subregisters. Any existing subreg indices on the original instruction are preserved or composed with the new subreg index. Also substitute multiple operands mentioning the original register by using the new MachineInstr::substituteRegister() function. This is necessary because there will soon be <imp-def> operands added to non read-modify-write partial definitions. This instruction: %reg1234:foo = FLAP %reg1234<imp-def> will reMaterialize(%reg3333, bar) like this: %reg3333:bar-foo = FLAP %reg333:bar<imp-def> Finally, replace the TargetRegisterInfo pointer argument with a reference to indicate that it cannot be NULL. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105358 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up 80 column violations. No functional change.Jim Grosbach2010-06-0219-50/+64
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105350 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the TargetRegisterClass member from CalleeSavedInfoRafael Espindola2010-06-021-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105344 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename canCombinedSubRegIndex method to something more grammatically correctBob Wilson2010-06-022-9/+10
| | | | | | | and tidy up the comment describing it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105339 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace ARM's getCalleeSavedRegClasses with a simpler solutionRafael Espindola2010-06-022-94/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105335 91177308-0d34-0410-b5e6-96231b3b80d8
* Some A9 load/store cleanupsAnton Korobeynikov2010-05-291-41/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105109 91177308-0d34-0410-b5e6-96231b3b80d8
* Some rough approximations for load/stores on A9Anton Korobeynikov2010-05-291-0/+59
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105108 91177308-0d34-0410-b5e6-96231b3b80d8
* NEON/VFP stuff can be issued only via Pipe1 on A9Anton Korobeynikov2010-05-291-87/+87
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105107 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some integer instruction itineraries for A9Anton Korobeynikov2010-05-291-0/+55
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105106 91177308-0d34-0410-b5e6-96231b3b80d8
* Schedule high latency instructions for latency reduction even if they are ↵Evan Cheng2010-05-281-1/+19
| | | | | | not vfp / NEON instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105060 91177308-0d34-0410-b5e6-96231b3b80d8
* correct retattrJim Grosbach2010-05-281-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104980 91177308-0d34-0410-b5e6-96231b3b80d8
* Cosmetic cleanup. No functional change.Jim Grosbach2010-05-282-18/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104974 91177308-0d34-0410-b5e6-96231b3b80d8
* make sure accesses to set up the jmpbuf don't get moved after it by the ↵Jim Grosbach2010-05-283-7/+10
| | | | | | scheduler. Add a missing \n. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104967 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the cc_out operand for t2RSBrs instructions. I missed this when I changedBob Wilson2010-05-281-2/+2
| | | | | | | | the instruction class for t2RSB to add that operand in svn r104582. Radar 8033757. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104907 91177308-0d34-0410-b5e6-96231b3b80d8
* Update the saved stack pointer in the sjlj function context following eitherJim Grosbach2010-05-275-19/+10
| | | | | | | | an alloca() or an llvm.stackrestore(). rdar://8031573 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104900 91177308-0d34-0410-b5e6-96231b3b80d8
* Use report_fatal_error, not llvm_unreachable.Evan Cheng2010-05-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104899 91177308-0d34-0410-b5e6-96231b3b80d8
* back out 104862/104869. Can reuse stacksave after all. Very cool.Jim Grosbach2010-05-272-9/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104897 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm can't correctly support 'H', 'Q' and 'R' modifiers. Just mark it an error.Evan Cheng2010-05-271-18/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104891 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some bad fall-throughs in a switch statement. Both the 'Q' and 'R' casesBob Wilson2010-05-271-11/+17
| | | | | | | | should fall through to the 'H' case, but instead 'Q' was falling through to 'R' so that it would do the wrong thing for a big-endian ARM target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104883 91177308-0d34-0410-b5e6-96231b3b80d8
* add ISD::STACKADDR to get the current stack pointer. Will be used by sjlj EHJim Grosbach2010-05-272-0/+9
| | | | | | to update the jmpbuf in the presence of VLAs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104862 91177308-0d34-0410-b5e6-96231b3b80d8
* Give SubRegIndex names to all ARM subregisters. This will be required byJakob Stoklund Olesen2010-05-261-14/+36
| | | | | | TableGen shortly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104754 91177308-0d34-0410-b5e6-96231b3b80d8
* Adjust eh.sjlj.setjmp to properly have a chain and to have an opcode entry inJim Grosbach2010-05-263-7/+15
| | | | | | | | ISD::. No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104734 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-99/+20
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
* Coding style change (Adding 1 missing space.)Shih-wei Liao2010-05-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104670 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding the missing implementation for ARM::SBFX and ARM::UBFX.Shih-wei Liao2010-05-261-1/+13
| | | | | | | Fixing http://llvm.org/bugs/show_bug.cgi?id=7225. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104667 91177308-0d34-0410-b5e6-96231b3b80d8
* fix off by 1 (insn) error in eh.sjlj.setjmp thumb code sequence.Jim Grosbach2010-05-262-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104661 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-20/+99
| | | | | | This reverts commit 104654. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-99/+20
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
* Adding the missing implementation of Bitfield's "clear" and "insert".Shih-wei Liao2010-05-261-4/+9
| | | | | | | Fixing http://llvm.org/bugs/show_bug.cgi?id=7222. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104653 91177308-0d34-0410-b5e6-96231b3b80d8
* To handle s* registers in emitVFPLoadStoreMultipleInstruction().Shih-wei Liao2010-05-261-7/+12
| | | | | | | Fixing http://llvm.org/bugs/show_bug.cgi?id=7221. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104652 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove NumberHack entirely.Jakob Stoklund Olesen2010-05-251-21/+21
| | | | | | | SubRegIndex instances are now numbered uniquely the same way Register instances are - in lexicographical order by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing implementation to the materialization of VFP misc. instructions ↵Zonr Chang2010-05-251-0/+43
| | | | | | (vmrs, vmsr and vmov (immediate)) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104588 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to MOVimm32 using movt/movw for ARM JITZonr Chang2010-05-253-2/+113
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104587 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow t2MOVsrl_flag and t2MOVsra_flag instructions to be predicated.Bob Wilson2010-05-251-6/+6
| | | | | | | | I don't know of any particular reason why that would be important, but neither can I see any reason to disallow it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104583 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up instruction classes for Thumb2 RSB instructions to be consistent withBob Wilson2010-05-251-15/+15
| | | | | | | | Thumb2 ADD and SUB instructions: allow RSB instructions be changed to set the condition codes, and allow RSBS instructions to be predicated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104582 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up indentation.Bob Wilson2010-05-251-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104580 91177308-0d34-0410-b5e6-96231b3b80d8
* Use enums instead of literals in the ARM backend.Jakob Stoklund Olesen2010-05-252-18/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104573 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch SubRegSet to using symbolic SubRegIndicesJakob Stoklund Olesen2010-05-241-77/+77
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104571 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow Thumb2 MVN instructions to set condition codes. The immediate operandBob Wilson2010-05-241-5/+5
| | | | | | | version of t2MVN already allowed that, but not the register versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104570 91177308-0d34-0410-b5e6-96231b3b80d8
* Lose the dummiesJakob Stoklund Olesen2010-05-241-22/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104564 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the tablegen RegisterClass field SubRegClassList with an alist-like dataJakob Stoklund Olesen2010-05-241-47/+42
| | | | | | | | | | | structure that represents a mapping without any dependencies on SubRegIndex numbering. This brings us closer to being able to remove the explicit SubRegIndex numbering, and it is now possible to specify any mapping without inventing *_INVALID register classes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104563 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up some extra whitespace.Bob Wilson2010-05-241-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104544 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb2 RSBS instructions were being printed without the 'S' suffix.Bob Wilson2010-05-241-6/+4
| | | | | | | | Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR output and 'S' suffix in the same way as T2I_bin_s_irs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104531 91177308-0d34-0410-b5e6-96231b3b80d8
* LR is in GPR, not tGPR even in Thumb1 mode.Evan Cheng2010-05-241-4/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104518 91177308-0d34-0410-b5e6-96231b3b80d8
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