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* Rename a parameter to avoid confusion with a local variableMatt Beaumont-Gay2010-11-101-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118656 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit the warning about the register list not being in ascending order only once.Bill Wendling2010-11-091-5/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118653 91177308-0d34-0410-b5e6-96231b3b80d8
* s/std::vector/SmallVector/Bill Wendling2010-11-091-12/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118648 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete the allocated vector.Bill Wendling2010-11-091-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118644 91177308-0d34-0410-b5e6-96231b3b80d8
* Define the subtarget feature for the architecture version,Bob Wilson2010-11-091-15/+40
| | | | | | | as derived from the target triple. This is important for enabling features that are implied based on the architecture version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118643 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not use MEMBARRIER_MCR for any Thumb code.Bob Wilson2010-11-091-2/+2
| | | | | | | | | It is only supported for ARM code. Normally Thumb2 code would use DMB instead, but depending on how the compiler is invoked (e.g., -mattr=-db) that might be disabled. This prevents a "cannot select MEMBARRIER_MCR" error in that situation. Radar 8644195 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118642 91177308-0d34-0410-b5e6-96231b3b80d8
* Two types of instructions have register lists:Bill Wendling2010-11-091-56/+32
| | | | | | | | | | | | * LDM, et al, uses a bit mask to indicate the register list. * VLDM, et al, uses a base register plus number. The LDM instructions may be non-contiguous, but the VLDM ones must be contiguous. Those are semantic checks that should be done later in the compiler. Also postpone the creation of the bit mask until it's needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118640 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the ARMConstantPoolValue modifier string to an enumeration. This willJim Grosbach2010-11-094-17/+42
| | | | | | help in MC'izing the references that use them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118633 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle ARM constant pool values that need an explicit reference to the '.'Jim Grosbach2010-11-091-1/+9
| | | | | | pseudo-label. (TLS stuff). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118609 91177308-0d34-0410-b5e6-96231b3b80d8
* Trailing whitespace.Jim Grosbach2010-11-091-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118606 91177308-0d34-0410-b5e6-96231b3b80d8
* Further MCize ARM constant pool values. This allows basic PIC references forJim Grosbach2010-11-091-67/+83
| | | | | | object file emission. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118601 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encoding of Rt to ARM LDR/STR w/ reg+reg offset encoding.Jim Grosbach2010-11-091-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118600 91177308-0d34-0410-b5e6-96231b3b80d8
* For ARM load/store instructions, encode [reg+reg] with no shifter immediate asJim Grosbach2010-11-091-0/+3
| | | | | | a left shift by zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM .word data fixups don't need an adjustment.Jim Grosbach2010-11-091-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118586 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encoder method for ARM load/store shifted register offset operands.Jim Grosbach2010-11-093-1/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118513 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for a few simple fixups to the ARM Darwin asm backend. This allowsJim Grosbach2010-11-092-10/+36
| | | | | | | | | | | | | | | | constant pool references and global variable refernces to resolve properly for object file generation. For example, int x; void foo(unsigned a, unsigned *p) { p[a] = x; } can now be successfully compiled directly to an (ARM mode) object file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118469 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r118457 and r118458. These won't hold for GPRs.Bill Wendling2010-11-092-6/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118462 91177308-0d34-0410-b5e6-96231b3b80d8
* Get the register and count from the register list operands.Bill Wendling2010-11-081-8/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118458 91177308-0d34-0410-b5e6-96231b3b80d8
* reglist has two operands.Bill Wendling2010-11-081-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118457 91177308-0d34-0410-b5e6-96231b3b80d8
* The "addRegListOperands()" function returns the start register and the totalBill Wendling2010-11-081-15/+21
| | | | | | | number of registers in the list. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118456 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for ARM's specialized vector-compare-against-zero instructions.Owen Anderson2010-11-083-24/+68
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
* Add "write back" bit encoding.Bill Wendling2010-11-081-8/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118446 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 118422 in search of bot verdancy.Dale Johannesen2010-11-082-78/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118429 91177308-0d34-0410-b5e6-96231b3b80d8
* Support -mcpu=cortex-a8 in ARM attributes - Has Fixme. 1 Test modified.Jason W Kim2010-11-082-10/+78
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118422 91177308-0d34-0410-b5e6-96231b3b80d8
* Complete listing of ARM/MC/ELF relocation enumsJason W Kim2010-11-081-3/+134
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118413 91177308-0d34-0410-b5e6-96231b3b80d8
* Make RegList an ASM operand so that TableGen will generate code for it. This isBill Wendling2010-11-081-2/+7
| | | | | | | an initial implementation and may change once reglists are fully fleshed out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118390 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert.Bill Wendling2010-11-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118389 91177308-0d34-0410-b5e6-96231b3b80d8
* In this context, a reglist is a reg.Bill Wendling2010-11-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118375 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for parsing register lists. We can't use a bitfield to keep track ofBill Wendling2010-11-061-22/+64
| | | | | | | | | | | | the registers, because the register numbers may be much greater than the number of bits available in the machine's register. I extracted the register list verification code out of the actual parsing of the registers. This made checking for errors much easier. It also limits the number of warnings that would be emitted for cascading infractions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118363 91177308-0d34-0410-b5e6-96231b3b80d8
* Return the base register of a register list for the "getReg()" method. This isBill Wendling2010-11-061-3/+8
| | | | | | | | to satisfy the ClassifyOperand method of the Asm matcher without having to add a RegList type to every back-end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118360 91177308-0d34-0410-b5e6-96231b3b80d8
* General cleanup:Bill Wendling2010-11-061-36/+21
| | | | | | | | - Make ARMOperand a class so that some things are internal to the class. - Reformatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118357 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a RegList (register list) object to ARMOperand. It will be used soon to holdBill Wendling2010-11-061-1/+38
| | | | | | | | (surprise!) a list of registers. Register lists are consecutive, so we only need to record the start register plus the number of registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118351 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix grammar.Bill Wendling2010-11-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118341 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix grammar.Bill Wendling2010-11-061-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118340 91177308-0d34-0410-b5e6-96231b3b80d8
* MatchRegisterName() returns 0 if it can't match the register.Bill Wendling2010-11-061-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118339 91177308-0d34-0410-b5e6-96231b3b80d8
* Use TryParseRegister() instead of MatchRegisterName(). The former returns -1Bill Wendling2010-11-061-5/+2
| | | | | | | while the latter doesn't. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118338 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure we have movw on the target before using it.Eric Christopher2010-11-061-1/+1
| | | | | | | Fixes 8559. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118333 91177308-0d34-0410-b5e6-96231b3b80d8
* Hook up the '.code {16|32}' directive to the streamer.Jim Grosbach2010-11-051-2/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118310 91177308-0d34-0410-b5e6-96231b3b80d8
* Hook up the '.thumb_func' directive to the streamer.Jim Grosbach2010-11-051-3/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118307 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix past-o.Jim Grosbach2010-11-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118304 91177308-0d34-0410-b5e6-96231b3b80d8
* MC'ize the '.code 16' and '.thumb_func' ARM directives.Jim Grosbach2010-11-051-11/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118301 91177308-0d34-0410-b5e6-96231b3b80d8
* Disallow the certain NEON modified-immediate forms when generating vorr or vbic.Owen Anderson2010-11-052-7/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118300 91177308-0d34-0410-b5e6-96231b3b80d8
* MC'ize simple ARMConstantValue entry emission (with a FIXME).Jim Grosbach2010-11-051-28/+37
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118295 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen and encoding support for the immediate form of vbic.Owen Anderson2010-11-053-6/+78
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118291 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable MachO writing for ARM/Darwin. Lots of stuff still doesn't workJim Grosbach2010-11-051-1/+0
| | | | | | (relocations, e.g.), but this will allow simple things to flow through. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118289 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow targets to specify the MachO CPUType/CPUSubtype information.Jim Grosbach2010-11-051-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118288 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FIXME.Jim Grosbach2010-11-051-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118280 91177308-0d34-0410-b5e6-96231b3b80d8
* In the calling convention logic, ValVT is always a legal type,Duncan Sands2010-11-042-8/+8
| | | | | | | | and as such can be represented by an MVT - the more complicated EVT is not needed. Use MVT for ValVT everywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118245 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix @llvm.prefetch isel. Selecting between pld / pldw using the first ↵Evan Cheng2010-11-043-38/+37
| | | | | | immediate rw. There is currently no intrinsic that matches to pli. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118237 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ARM fixup info for load/store label references. Probably will need a bit ofJim Grosbach2010-11-042-30/+79
| | | | | | | tweaking when we start using it for object file emission or JIT, but it's a start. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118221 91177308-0d34-0410-b5e6-96231b3b80d8
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