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path: root/lib/Target/Alpha/AlphaInstrInfo.td
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* Add support to tablegen for naming the nodes themselves, not just the operands, Nate Begeman2009-03-191-1/+1
| | | | | | | | in selectiondag patterns. This is required for the upcoming shuffle_vector rewrite, and as it turns out, cleans up a hack in the Alpha instruction info. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67286 91177308-0d34-0410-b5e6-96231b3b80d8
* silence warning when asserts disabled.Chris Lattner2008-12-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61013 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a sanity-check to tablegen to catch the case where isSimpleLoadDan Gohman2008-12-031-2/+6
| | | | | | | | | | is set but mayLoad is not set. Fix all the problems this turned up. Change code to not use isSimpleLoad instead of mayLoad unless it really wants isSimpleLoad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60459 91177308-0d34-0410-b5e6-96231b3b80d8
* This shouldn't be necessaryAndrew Lenharth2008-11-111-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59090 91177308-0d34-0410-b5e6-96231b3b80d8
* Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's asChris Lattner2008-10-111-2/+2
| | | | | | | | | parameters instead of raw Constants. This prevents the constants from being selected by the isel pass, fixing PR2735. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-121-32/+39
| | | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
* Tablegen generated code already tests the opcode value, so it's notDan Gohman2008-08-201-5/+3
| | | | | | | necessary to use dyn_cast in these predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55055 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename SDOperand to SDValue.Dan Gohman2008-07-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
* Added MemOperands to Atomic operations since Atomics touches memory.Mon P Wang2008-06-251-4/+4
| | | | | | | | | Added abstract class MemSDNode for any Node that have an associated MemOperand Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and atomic.lss => atomic.load.sub git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-9/+0
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
* Final de-tabification.Bill Wendling2008-02-271-18/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47663 91177308-0d34-0410-b5e6-96231b3b80d8
* Atomic op support. If any gcc test uses __sync builtins, it might start ↵Andrew Lenharth2008-02-211-5/+29
| | | | | | failing on archs that haven't implemented them yet git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47430 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm.memory.barrier, and impl for x86 and alphaAndrew Lenharth2008-02-161-1/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47204 91177308-0d34-0410-b5e6-96231b3b80d8
* rename SDTRet -> SDTNone.Chris Lattner2008-01-151-1/+1
| | | | | | | Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8
* get def use info more correct.Chris Lattner2008-01-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45821 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-061-31/+31
| | | | | | | | | | | | instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45654 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always ↵Evan Cheng2007-12-121-0/+2
| | | | | | re-materializable and they should not be spilled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8
* something wrong with this optAndrew Lenharth2007-11-271-12/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44370 91177308-0d34-0410-b5e6-96231b3b80d8
* Unifacalize the CALLSEQ{START,END} stuff.Bill Wendling2007-11-131-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44045 91177308-0d34-0410-b5e6-96231b3b80d8
* Unify CALLSEQ_{START,END}. They take 4 parameters: the chain, two stackBill Wendling2007-11-131-7/+13
| | | | | | | | | | | | adjustment fields, and an optional flag. If there is a "dynamic_stackalloc" in the code, make sure that it's bracketed by CALLSEQ_START and CALLSEQ_END. If not, then there is the potential for the stack to be changed while the stack's being used by another instruction (like a call). This can only result in tears... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44037 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a flag for indirect branch instructions.Owen Anderson2007-11-121-2/+1
| | | | | | | Target maintainers: please check that the instructions for your target are correctly marked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-111-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
* No more noResults.Evan Cheng2007-07-211-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-31/+39
| | | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
* Use this nifty Constraints thing and fix the inverted conditional movesAndrew Lenharth2007-04-171-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36191 91177308-0d34-0410-b5e6-96231b3b80d8
* FTOIT and ITOFT are bit converts, and if we drop 21264s, are always availableAndrew Lenharth2007-01-241-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33492 91177308-0d34-0410-b5e6-96231b3b80d8
* Be sure to grab weak functions too, and make implicit defs commentsAndrew Lenharth2006-12-071-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32308 91177308-0d34-0410-b5e6-96231b3b80d8
* silence warnings.Chris Lattner2006-11-031-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31394 91177308-0d34-0410-b5e6-96231b3b80d8
* fix 2006-11-01-vastart.llAndrew Lenharth2006-11-021-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31371 91177308-0d34-0410-b5e6-96231b3b80d8
* more shotenningAndrew Lenharth2006-10-311-113/+75
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31331 91177308-0d34-0410-b5e6-96231b3b80d8
* Let us play simplify the td file (and fix a few missed sub and mul patterns).Andrew Lenharth2006-10-311-83/+55
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31322 91177308-0d34-0410-b5e6-96231b3b80d8
* Add all that branch mangling niftinessAndrew Lenharth2006-10-311-105/+158
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31313 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng2006-10-131-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
* adjcallstack up/down clobbers the spChris Lattner2006-10-121-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30910 91177308-0d34-0410-b5e6-96231b3b80d8
* Use cute tblgen tricks to make zap handling more powerful. Specifically,Chris Lattner2006-10-111-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | when the dag combiner simplifies an and mask, notice this and allow those bits to be missing from the zap mask. This compiles Alpha/zapnot4.ll into: sll $16,3,$0 zapnot $0,3,$0 ret $31,($26),1 instead of: ldah $0,1($31) lda $0,-8($0) sll $16,3,$1 and $1,$0,$0 ret $31,($26),1 It would be *really* nice to replace the hunk of code in the AlphaISelDAGToDAG.cpp file that matches (and (srl (x, C), c2) into (SRL (ZAPNOTi)) with a similar pattern, but I've spent enough time poking at alpha. Make andrew will do this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30875 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead/redundant instructions. These are handled by ZAPNOTiChris Lattner2006-10-111-6/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30872 91177308-0d34-0410-b5e6-96231b3b80d8
* Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng2006-10-091-18/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
* catch constants more oftenAndrew Lenharth2006-09-201-0/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30534 91177308-0d34-0410-b5e6-96231b3b80d8
* Jump tables on AlphaAndrew Lenharth2006-09-181-1/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30463 91177308-0d34-0410-b5e6-96231b3b80d8
* CALLSEQ_* produces chain even if that's not needed.Evan Cheng2006-08-111-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29603 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a duplicate pattern/Evan Cheng2006-07-311-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29413 91177308-0d34-0410-b5e6-96231b3b80d8
* Let the alpha breakage begin. First Formals and RET. next CallsAndrew Lenharth2006-06-121-1/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28753 91177308-0d34-0410-b5e6-96231b3b80d8
* ignore ordered/unordered for nowAndrew Lenharth2006-06-041-0/+120
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28679 91177308-0d34-0410-b5e6-96231b3b80d8
* support x * (c1 + c2) where c1 and c2 are pow2s. special case for c2 == 4Andrew Lenharth2006-04-031-9/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27370 91177308-0d34-0410-b5e6-96231b3b80d8
* mul by const conversion sequences. more coming soonAndrew Lenharth2006-04-031-1/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27368 91177308-0d34-0410-b5e6-96231b3b80d8
* fcopysign for mixed modeAndrew Lenharth2006-03-091-1/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26651 91177308-0d34-0410-b5e6-96231b3b80d8
* alpha and llvm have different oppinions on which arg is the sign bitAndrew Lenharth2006-03-091-10/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26647 91177308-0d34-0410-b5e6-96231b3b80d8
* Alpha Scheduling classesAndrew Lenharth2006-03-091-191/+191
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26643 91177308-0d34-0410-b5e6-96231b3b80d8
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