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* Remove the CellSPU port.Eric Christopher2012-11-141-449/+0
| | | | | | | Approved by Chris Lattner. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167984 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove tabs.Bill Wendling2012-07-191-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160476 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-16/+16
| | | | | | since they are equivalent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change ↵Craig Topper2012-04-201-40/+36
| | | | | | since they are equivalent. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155186 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a iterator out of bounds error, that triggers rarely.Kalle Raiskila2011-10-111-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141665 91177308-0d34-0410-b5e6-96231b3b80d8
* Move TargetRegistry and TargetSelect from Target to Support where they belong.Evan Cheng2011-08-241-1/+1
| | | | | | | These are strictly utilities for registering targets and components. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138450 91177308-0d34-0410-b5e6-96231b3b80d8
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-12/+0
| | | | | | | registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-1/+12
| | | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
* Hide the call to InitMCInstrInfo into tblgen generated ctor.Evan Cheng2011-07-011-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134244 91177308-0d34-0410-b5e6-96231b3b80d8
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-281-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134030 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-281-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134024 91177308-0d34-0410-b5e6-96231b3b80d8
* Add branch hinting for SPU. Kalle Raiskila2011-02-281-3/+61
| | | | | | | | The implemented algorithm is overly simplistic (just speculate all branches are taken)- this is work in progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126651 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs ↵Anton Korobeynikov2011-01-101-2/+2
| | | | | | and fixes here and there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123170 91177308-0d34-0410-b5e6-96231b3b80d8
* Various bits of framework needed for precise machine-level selectionAndrew Trick2010-12-241-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | DAG scheduling during isel. Most new functionality is currently guarded by -enable-sched-cycles and -enable-sched-hazard. Added InstrItineraryData::IssueWidth field, currently derived from ARM itineraries, but could be initialized differently on other targets. Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is active, and if so how many cycles of state it holds. Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry into the scheduler's available queue. ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to get information about it's SUnits, provides RecedeCycle for bottom-up scheduling, correctly computes scoreboard depth, tracks IssueCount, and considers potential stall cycles when checking for hazards. ScheduleDAGRRList now models machine cycles and hazards (under flags). It tracks MinAvailableCycle, drives the hazard recognizer and priority queue's ready filter, manages a new PendingQueue, properly accounts for stall cycles, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the isMoveInstr() hook.Jakob Stoklund Olesen2010-07-161-142/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108567 91177308-0d34-0410-b5e6-96231b3b80d8
* RISC architectures get their memory operand folding for free.Jakob Stoklund Olesen2010-07-111-82/+0
| | | | | | | | The only folding these load/store architectures can do is converting COPY into a load or store, and the target independent part of foldMemoryOperand already knows how to do that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace copyRegToReg with copyPhysReg for CellSPU.Jakob Stoklund Olesen2010-07-111-28/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108084 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark the SPU 'lr' instruction to never have side effects. Kalle Raiskila2010-06-211-2/+0
| | | | | | | | | | This allows the fast regiser allocator to remove redundant register moves. Update a set of tests that depend on the register allocator to be linear scan. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106420 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a DebugLoc parameter to TargetInstrInfo::InsertBranch(). ThisStuart Hastings2010-06-171-7/+6
| | | | | | | | | | | | | addresses a longstanding deficiency noted in many FIXMEs scattered across all the targets. This effectively moves the problem up one level, replacing eleven FIXMEs in the targets with eight FIXMEs in CodeGen, plus one path through FastISel where we actually supply a DebugLoc, fixing Radar 7421831. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106243 91177308-0d34-0410-b5e6-96231b3b80d8
* Make SPU backend not assert on jump tables.Kalle Raiskila2010-05-111-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103466 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a DebugLoc argument to TargetInstrInfo::copyRegToReg, so that itDan Gohman2010-05-061-4/+2
| | | | | | | doesn't have to guess. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103194 91177308-0d34-0410-b5e6-96231b3b80d8
* Add argument TargetRegisterInfo to loadRegFromStackSlot and storeRegToStackSlot.Evan Cheng2010-05-061-6/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103193 91177308-0d34-0410-b5e6-96231b3b80d8
* use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()Chris Lattner2010-04-021-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach AnalyzeBranch, RemoveBranch and the branchDale Johannesen2010-04-021-1/+14
| | | | | | | | | folder to be tolerant of debug info following the branch(es) at the end of a block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100168 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the target hook TargetInstrInfo::BlockHasNoFallThrough in favor ofDan Gohman2009-12-051-4/+0
| | | | | | | | MachineBasicBlock::canFallThrough(), which is target-independent and more thorough. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90634 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove Streams.h from the targets.Benjamin Kramer2009-08-231-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79853 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused member functions.Eli Friedman2009-07-241-74/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76960 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.Torok Edwin2009-07-141-4/+4
| | | | | | | | | | This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement changes from Chris's feedback.Torok Edwin2009-07-081-12/+7
| | | | | | | Finish converting lib/Target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle IMPLICIT_DEF with isUndef operand marker, part 2. This patch moves ↵Evan Cheng2009-07-011-2/+5
| | | | | | the code to annotate machineoperands to LiveIntervalAnalysis. It also add markers for implicit_def that define physical registers. The rest, is just a lot of details. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74580 91177308-0d34-0410-b5e6-96231b3b80d8
* Remember to set def-flag on register loaded from stack slot in CellSPU.Jakob Stoklund Olesen2009-05-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71934 91177308-0d34-0410-b5e6-96231b3b80d8
* Change MachineInstrBuilder::addReg() to take a flag instead of a list ofBill Wendling2009-05-131-4/+4
| | | | | | | | | | | | | booleans. This gives a better indication of what the "addReg()" is doing. Remembering what all of those booleans mean isn't easy, especially if you aren't spending all of your time in that code. I took Jakob's suggestion and made it illegal to pass in "true" for the flag. This should hopefully prevent any unintended misuse of this (by reverting to the old way of using addReg()). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71722 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-03-171-4/+1
| | | | | | | | | | | | | | - Fix fabs, fneg for f32 and f64. - Use BuildVectorSDNode.isConstantSplat, now that the functionality exists - Continue to improve i64 constant lowering. Lower certain special constants to the constant pool when they correspond to SPU's shufb instruction's special mask values. This avoids the overhead of performing a shuffle on a zero-filled vector just to get the special constant when the memory load suffices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67067 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-03-161-1/+6
| | | | | | | | Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the llvm-gcc bootstrap a bit further along. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67048 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out the code to add a MachineOperand to a MachineInstrBuilder.Dan Gohman2009-02-181-18/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove non-DebugLoc versions of BuildMI from Alpha and Cell.Dale Johannesen2009-02-131-4/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64433 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate a couple of non-DebugLoc BuildMI variants.Dale Johannesen2009-02-121-2/+4
| | | | | | | | Modify callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
* Move debug loc info along when the spiller creates new instructions.Bill Wendling2009-02-121-16/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64342 91177308-0d34-0410-b5e6-96231b3b80d8
* Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nastyEvan Cheng2009-02-091-2/+4
| | | | | | | | | suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-061-8/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
* Untabify code.Scott Michel2009-01-261-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62991 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-261-2/+2
| | | | | | | | | | | | | | | | | - Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). <rant>DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen.</rant> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-211-1/+8
| | | | | | | | | | | | | | - Ensure that (operation) legalization emits proper FDIV libcall when needed. - Fix various bugs encountered during llvm-spu-gcc build, along with various cleanups. - Start supporting double precision comparisons for remaining libgcc2 build. Discovered interesting DAGCombiner feature, which is currently solved via custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner insists on inserting one anyway.) - Update README. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62664 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-1/+4
| | | | | | sub-register indices as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix off-by-one error in traversing an array; this fixes a test.Misha Brukman2009-01-071-1/+1
| | | | | | | The error was reported by gcc-4.3.0 during compilation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61896 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-061-1/+26
| | | | | | | | | | | | | - Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we need to ensure that i128 is 16-byte aligned in real life), and 128 zero- extends are supported. - New td file: SPU128InstrInfo.td: this is where all new i128 support should be put in the future. - Continue to hammer on i64 operations and test cases; ensure that the only remaining problem will be i64 mul. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61784 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-031-56/+92
| | | | | | | | | | - Remove custom lowering for BRCOND - Add remaining functionality for branches in SPUInstrInfo, such as branch condition reversal and load/store folding. Updated BrCond test to reflect branch reversal. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61597 91177308-0d34-0410-b5e6-96231b3b80d8
* - Make copyRegToReg use the "LR" assembler synonym for "OR". Makes findingScott Michel2009-01-021-38/+50
| | | | | | | | register copies a little easier to pick out from the output. - Fix bug 3192. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61591 91177308-0d34-0410-b5e6-96231b3b80d8
* - Start moving target-dependent nodes that could be represented by anScott Michel2008-12-301-15/+14
| | | | | | | | | | | | | | instruction sequence and cannot ordinarily be simplified by DAGcombine into the various target description files or SPUDAGToDAGISel.cpp. This makes some 64-bit operations legal. - Eliminate target-dependent ISD enums. - Update tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61508 91177308-0d34-0410-b5e6-96231b3b80d8
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