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* Use CHAR_BIT instead of hard-coding 8 in several places where itDan Gohman2009-04-011-1/+1
| | | | | | | | is appropriate. This helps visually differentiate host-oriented calculations from target-oriented calculations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68227 91177308-0d34-0410-b5e6-96231b3b80d8
* fix warning in -asserts mode.Chris Lattner2009-03-261-4/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67739 91177308-0d34-0410-b5e6-96231b3b80d8
* CodeGen still defaults to non-verbose asm, but llc now overrides it and ↵Evan Cheng2009-03-254-10/+10
| | | | | | default to verbose. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67668 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-03-172-16/+16
| | | | | | | Revert inadvertent mis-fix of fneg. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67084 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-03-175-488/+417
| | | | | | | | | | | | | | - Fix fabs, fneg for f32 and f64. - Use BuildVectorSDNode.isConstantSplat, now that the functionality exists - Continue to improve i64 constant lowering. Lower certain special constants to the constant pool when they correspond to SPU's shufb instruction's special mask values. This avoids the overhead of performing a shuffle on a zero-filled vector just to get the special constant when the memory load suffices. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67067 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-03-163-98/+114
| | | | | | | | Incorporate Tilmann's 128-bit operation patch. Evidently, it gets the llvm-gcc bootstrap a bit further along. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67048 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some significant problems with constant pools that resulted in ↵Evan Cheng2009-03-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants. 2. MachineConstantPool alignment field is also a log2 value. 3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values. 4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries. 5. Asm printer uses expensive data structure multimap to track constant pool entries by sections. 6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic. Solutions: 1. ConstantPoolSDNode alignment field is changed to keep non-log2 value. 2. MachineConstantPool alignment field is also changed to keep non-log2 value. 3. Functions that create ConstantPool nodes are passing in non-log2 alignments. 4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT. 5. Asm printer uses cheaper data structure to group constant pool entries. 6. Asm printer compute entry offsets after grouping is done. 7. Change JIT code to compute entry offsets on the fly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66875 91177308-0d34-0410-b5e6-96231b3b80d8
* It makes no sense to have a ODR version of commonDuncan Sands2009-03-111-2/+1
| | | | | | | linkage, so remove it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66690 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce new linkage types linkonce_odr, weak_odr, common_odrDuncan Sands2009-03-071-6/+11
| | | | | | | | | | | | | | | | | | | | | | and extern_weak_odr. These are the same as the non-odr versions, except that they indicate that the global will only be overridden by an *equivalent* global. In C, a function with weak linkage can be overridden by a function which behaves completely differently. This means that IP passes have to skip weak functions, since any deductions made from the function definition might be wrong, since the definition could be replaced by something completely different at link time. This is not allowed in C++, thanks to the ODR (One-Definition-Rule): if a function is replaced by another at link-time, then the new function must be the same as the original function. If a language knows that a function or other global can only be overridden by an equivalent global, it can give it the weak_odr linkage type, and the optimizers will understand that it is alright to make deductions based on the function body. The code generators on the other hand map weak and weak_odr linkage to the same thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66339 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bunch of Doxygen syntax issues. Escape special characters,Dan Gohman2009-03-031-1/+1
| | | | | | | and put @file directives on their own comment line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65920 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert BuildVectorSDNode related patches: 65426, 65427, and 65296.Evan Cheng2009-02-252-45/+47
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65482 91177308-0d34-0410-b5e6-96231b3b80d8
* Overhaul my earlier submission due to feedback. It's a large patch, but most ofBill Wendling2009-02-243-18/+18
| | | | | | | | | | | | | them are generic changes. - Use the "fast" flag that's already being passed into the asm printers instead of shoving it into the DwarfWriter. - Instead of calling "MI->getParent()->getParent()" for every MI, set the machine function when calling "runOnMachineFunction" in the asm printers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65379 91177308-0d34-0410-b5e6-96231b3b80d8
* Propagate debug loc info through prologue/epilogue.Bill Wendling2009-02-231-2/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65298 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce the BuildVectorSDNode class that encapsulates the ISD::BUILD_VECTORScott Michel2009-02-222-47/+45
| | | | | | | | | | instruction. The class also consolidates the code for detecting constant splats that's shared across PowerPC and the CellSPU backends (and might be useful for other backends.) Also introduces SelectionDAG::getBUID_VECTOR() for generating new BUILD_VECTOR nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65296 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out the code to add a MachineOperand to a MachineInstrBuilder.Dan Gohman2009-02-181-18/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64891 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove non-DebugLoc versions of BuildMI from Alpha and Cell.Dale Johannesen2009-02-132-24/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64433 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate a couple of non-DebugLoc BuildMI variants.Dale Johannesen2009-02-121-2/+4
| | | | | | | | Modify callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64409 91177308-0d34-0410-b5e6-96231b3b80d8
* Move debug loc info along when the spiller creates new instructions.Bill Wendling2009-02-121-16/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64342 91177308-0d34-0410-b5e6-96231b3b80d8
* Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nastyEvan Cheng2009-02-092-3/+6
| | | | | | | | | suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
* Use getDebugLoc forwarder instead of getNode()->getDebugLoc.Dale Johannesen2009-02-071-2/+2
| | | | | | | | No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64026 91177308-0d34-0410-b5e6-96231b3b80d8
* Needs this file too.Dale Johannesen2009-02-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63993 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of the last non-DebugLoc versions of getNode!Dale Johannesen2009-02-071-3/+3
| | | | | | | | | | | | | | Many targets build placeholder nodes for special operands, e.g. GlobalBaseReg on X86 and PPC for the PIC base. There's no sensible way to associate debug info with these. I've left them built with getNode calls with explicit DebugLoc::getUnknownLoc operands. I'm not too happy about this but don't see a good improvement; I considered adding a getPseudoOperand or something, but it seems to me that'll just make it harder to read. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63992 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove more non-DebugLoc versions of getNode.Dale Johannesen2009-02-061-37/+49
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63969 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-064-12/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of one more non-DebugLoc getNode andDale Johannesen2009-02-063-131/+150
| | | | | | | | | its corresponding getTargetNode. Lots of caller changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63904 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove non-DebugLoc forms of CopyToReg and CopyFromReg.Dale Johannesen2009-02-041-35/+41
| | | | | | | | Adjust callers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63789 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove non-DebugLoc versions of getLoad and getStore.Dale Johannesen2009-02-042-43/+54
| | | | | | | | Adjust the many callers of those versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63767 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some more non-DebugLoc versions of constructionDale Johannesen2009-02-041-23/+25
| | | | | | | | functions, with callers adjusted to fit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63705 91177308-0d34-0410-b5e6-96231b3b80d8
* Make LowerCallTo and LowerArguments take a DebugLocDale Johannesen2009-01-301-1/+2
| | | | | | | | argument. Adjust all callers and overloaded versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63444 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename getAnalysisToUpdate to getAnalysisIfAvailable.Duncan Sands2009-01-281-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63198 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-266-70/+75
| | | | | | | - Update DWARF debugging support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63059 91177308-0d34-0410-b5e6-96231b3b80d8
* Untabify code.pingbak2009-01-266-49/+49
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62991 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:pingbak2009-01-266-231/+468
| | | | | | | | | | | | | | | | | - Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). <rant>DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen.</rant> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62990 91177308-0d34-0410-b5e6-96231b3b80d8
* fix warning in release-asserts mode and spelling of assert.Chris Lattner2009-01-211-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62699 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-218-130/+313
| | | | | | | | | | | | | | - Ensure that (operation) legalization emits proper FDIV libcall when needed. - Fix various bugs encountered during llvm-spu-gcc build, along with various cleanups. - Start supporting double precision comparisons for remaining libgcc2 build. Discovered interesting DAGCombiner feature, which is currently solved via custom lowering (64-bit constants are not legal on CellSPU, but DAGCombiner insists on inserting one anyway.) - Update README. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62664 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-202-7/+9
| | | | | | sub-register indices as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
* Generalize the HazardRecognizer interface so that it can be usedDan Gohman2009-01-153-11/+14
| | | | | | | | to support MachineInstr-based scheduling in addition to SDNode-based scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62284 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the private linkage.Rafael Espindola2009-01-151-3/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
* Move a few containers out of ScheduleDAGInstrs::BuildSchedGraphDan Gohman2009-01-151-1/+1
| | | | | | | | | | | | and into the ScheduleDAGInstrs class, so that they don't get destructed and re-constructed for each block. This fixes a compile-time hot spot in the post-pass scheduler. To help facilitate this, tidy and do some minor reorganization in the scheduler constructor functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
* - Convert remaining i64 custom lowering into custom instruction emissionScott Michel2009-01-157-185/+333
| | | | | | | | | | | | | | sequences in SPUDAGToDAGISel.cpp and SPU64InstrInfo.td, killing custom DAG node types as needed. - i64 mul is now a legal instruction, but emits an instruction sequence that stretches tblgen and the imagination, as well as violating laws of several small countries and most southern US states (just kidding, but looking at a function with 80+ parameters is really weird and just plain wrong.) - Update tests as needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62254 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename getABITypeSize to getTypePaddedSize, asDuncan Sands2009-01-121-1/+1
| | | | | | | suggested by Chris. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62099 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed trailing whitespace from Makefiles.Misha Brukman2009-01-092-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61991 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert DwarfWriter into a pass.Devang Patel2009-01-081-7/+9
| | | | | | | Now Users request DwarfWriter through getAnalysisUsage() instead of creating an instance of DwarfWriter object directly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61955 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix off-by-one error in traversing an array; this fixes a test.Misha Brukman2009-01-071-1/+1
| | | | | | | The error was reported by gcc-4.3.0 during compilation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61896 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-067-61/+38
| | | | | | | | - Add preliminary support for v2i32; load/store generates the right code but there's a lot work to be done to make this vector type operational. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61829 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU: Update the READMEScott Michel2009-01-061-7/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61785 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-066-57/+213
| | | | | | | | | | | | | - Fix bugs 3194, 3195: i128 load/stores produce correct code (although, we need to ensure that i128 is 16-byte aligned in real life), and 128 zero- extends are supported. - New td file: SPU128InstrInfo.td: this is where all new i128 support should be put in the future. - Continue to hammer on i64 operations and test cases; ensure that the only remaining problem will be i64 mul. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61784 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-051-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-051-1/+111
| | | | | | | | - Teach SPU64InstrInfo.td about the remaining signed comparisons, update tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61672 91177308-0d34-0410-b5e6-96231b3b80d8
* CellSPU:Scott Michel2009-01-053-35/+82
| | | | | | | | | | | - Fix (brcond (setq ...)) bug, where BRNZ should have been used vice BRZ. - Kill unused/unnecessary nodes in SPUNodes.td - Beef out the i64operations.c test harness to use a lot of unaligned loads, test loops and LLVM loop/basic block optimizations; run the test harness successfully on real Cell hardware. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61664 91177308-0d34-0410-b5e6-96231b3b80d8
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