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* Hexagon: Add patterns to generate 'combine' instructions.Jyotsna Verma2013-05-141-0/+87
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181805 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Fix switch cases in HexagonVLIWPacketizer.cpp.Jyotsna Verma2013-05-101-39/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181624 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Set accessSize and addrMode on all load/store instructions.Jyotsna Verma2013-05-071-30/+60
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181324 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-061-149/+164
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181235 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting r180953Jyotsna Verma2013-05-021-164/+149
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180964 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add multiclass/encoding bits for the New-Value Jump instructions.Jyotsna Verma2013-05-021-149/+164
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180953 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for Jump instructions.Jyotsna Verma2013-05-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180885 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.Jyotsna Verma2013-04-231-97/+67
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180145 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Define relations for GP-relative instructions.Jyotsna Verma2013-04-231-15/+17
| | | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180144 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Remove duplicate instructions to handle global/immediate valuesJyotsna Verma2013-04-231-306/+55
| | | | | | | | for absolute/absolute-set addressing modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180120 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Set isPredicatedNew flag on predicate new instructions.Jyotsna Verma2013-04-121-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179388 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Set isPredicatedFlase flag for all the instructions with negated ↵Jyotsna Verma2013-04-121-10/+10
| | | | | | predication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179387 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for gp-relative instructions.Jyotsna Verma2013-03-281-655/+203
| | | | | | | | Remove noV4T gp-relative instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178246 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for aslh, asrh, sxtb, sxth, zxtb and zxth.Jyotsna Verma2013-03-261-158/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178032 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and ↵Jyotsna Verma2013-03-221-392/+345
| | | | | | word. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177747 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add patterns for zero extended loads from i1->i64.Jyotsna Verma2013-03-081-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176689 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add support to lower block address.Jyotsna Verma2013-03-071-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176637 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting patch 176508.Jyotsna Verma2013-03-051-5/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176513 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add support for lowering block address.Jyotsna Verma2013-03-051-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176508 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Set appropriate TSFlags to the loads/stores with global address toJyotsna Verma2013-02-151-33/+25
| | | | | | | | | | support constant extension. This patch doesn't introduce any functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175280 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for absolute addressing mode loads.Jyotsna Verma2013-02-141-74/+35
| | | | | | | | This patch doesn't introduce any functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175187 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use absolute addressing mode loads/stores for global+offset Jyotsna Verma2013-02-131-637/+117
| | | | | | | | instead of redefining separate instructions for them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175086 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use TFR_cond with cmpb.[eq,gt,gtu] to handleJyotsna Verma2013-02-051-0/+206
| | | | | | | | zext( set[ne,eq,gt,ugt] (...) ) type of dag patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174429 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Use multiclass for absolute addressing mode stores.Jyotsna Verma2013-02-051-102/+70
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174412 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add V4 compare instructions. Enable relationship mappingJyotsna Verma2013-02-051-16/+143
| | | | | | | | for the existing instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174389 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Add V4 combine instructions and some more Def Pats for V2.Jyotsna Verma2013-02-041-0/+80
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174331 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace LDriu*[bhdw]_indexed_V4 instructions with "def Pats".Jyotsna Verma2013-02-011-324/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174193 91177308-0d34-0410-b5e6-96231b3b80d8
* Add appropriate TSFlags to the instructions that must be always extended.Jyotsna Verma2013-02-011-148/+147
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174186 91177308-0d34-0410-b5e6-96231b3b80d8
* Use multiclass for post-increment store instructions.Jyotsna Verma2013-01-291-235/+56
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173816 91177308-0d34-0410-b5e6-96231b3b80d8
* Add constant extender support for MInst type instructions.Jyotsna Verma2013-01-291-52/+114
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173813 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove more unnecessary # operators with nothing to paste proceeding them.Craig Topper2013-01-071-18/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171702 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove # from the beginning and end of def names. The # is a paste operator ↵Craig Topper2013-01-071-24/+24
| | | | | | and should only be used with something to paste on either side. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171697 91177308-0d34-0410-b5e6-96231b3b80d8
* Add constant extender support to GP-relative load/store instructions.Jyotsna Verma2012-12-201-31/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170672 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TSFlags to ALU32 type instructions for constant-extender/Relationship maps.Jyotsna Verma2012-12-201-29/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170671 91177308-0d34-0410-b5e6-96231b3b80d8
* Use multiclass for new-value store instructions with MEMri operand.Jyotsna Verma2012-12-111-148/+46
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169814 91177308-0d34-0410-b5e6-96231b3b80d8
* Define new-value store instructions with base+immediate addressing modeJyotsna Verma2012-12-051-128/+53
| | | | | | | | using multiclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169432 91177308-0d34-0410-b5e6-96231b3b80d8
* Use multiclass to define store instructions with base+immediate offsetJyotsna Verma2012-12-051-138/+68
| | | | | | | | addressing mode and immediate stored value. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169408 91177308-0d34-0410-b5e6-96231b3b80d8
* Define store instructions with base+register offset addressing modeJyotsna Verma2012-12-041-352/+116
| | | | | | | | using multiclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169314 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns to define 'combine', 'tstbit', 'ct0/cl0' (count ↵Jyotsna Verma2012-12-041-6/+18
| | | | | | | | | | trailing/leading zeros) instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169287 91177308-0d34-0410-b5e6-96231b3b80d8
* Define store instructions with base+immediate offset addressing modeJyotsna Verma2012-12-031-84/+0
| | | | | | | | using multiclass. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169168 91177308-0d34-0410-b5e6-96231b3b80d8
* Use multiclass for the store instructions with MEMri operand.Jyotsna Verma2012-11-301-80/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168983 91177308-0d34-0410-b5e6-96231b3b80d8
* Use multiclass for the load instructions with 'base + register offset'Jyotsna Verma2012-11-301-277/+97
| | | | | | | | addressing mode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168976 91177308-0d34-0410-b5e6-96231b3b80d8
* Removing some unused instruction definitions from the Hexagon backend.Jyotsna Verma2012-11-201-74/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168388 91177308-0d34-0410-b5e6-96231b3b80d8
* Added multiclass for post-increment load instructions.Jyotsna Verma2012-11-141-102/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167974 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove variable_ops from call instructions in most targets.Jakob Stoklund Olesen2012-07-131-3/+3
| | | | | | | | Call instructions are no longer required to be variadic, and variable_ops should only be used for instructions that encode a variable number of arguments, like the ARM stm/ldm instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160189 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 156634 upon request until code improvement changes are made.Brendon Cahoon2012-05-141-192/+189
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156775 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon constant extender support.Brendon Cahoon2012-05-111-189/+192
| | | | | | | Patch by Jyotsna Verma. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156634 91177308-0d34-0410-b5e6-96231b3b80d8
* Update load/store instruction patterns in Hexagon V4.Sirish Pande2012-05-081-492/+492
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156411 91177308-0d34-0410-b5e6-96231b3b80d8
* Extensions of Hexagon V4 instructions.Sirish Pande2012-05-031-384/+2578
| | | | | | This adds new instructions for Hexagon V4 architecture. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156071 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r155365, r155366, and r155367. All three of these have regressionChandler Carruth2012-04-231-2538/+375
| | | | | | | | | | | test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155372 91177308-0d34-0410-b5e6-96231b3b80d8
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