aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Remove the Copied parameter from MemoryObject::readBytes.Benjamin Kramer2013-05-241-1/+1
| | | | | | | | | | There was exactly one caller using this API right, the others were relying on specific behavior of the default implementation. Since it's too hard to use it right just remove it and standardize on the default behavior. Defines away PR16132. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182636 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] DSP-ASE move from HI/LO register instructions.Akira Hatanaka2013-04-181-0/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179739 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix DSP instructions to have explicit accumulator register operands.Akira Hatanaka2013-03-301-9/+9
| | | | | | | | Check that instruction selection can select multiply-add/sub DSP instructions from a pattern that doesn't have intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178406 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the form field from Mips16 instruction formats and set thingsReed Kotler2013-02-141-0/+14
| | | | | | | | | | up so that we can apply the direct object emitter patch. This patch should be a nop right now and it's test is to not break what is already there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175126 91177308-0d34-0410-b5e6-96231b3b80d8
* This is a resubmittal. For some reason it broke the bots yesterdayJack Carter2013-01-171-0/+16
| | | | | | | | | | | | | | | but I cannot reproduce the problem and have scrubed my sources and even tested with llvm-lit -v --vg. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172685 91177308-0d34-0410-b5e6-96231b3b80d8
* reverting 172579Jack Carter2013-01-161-16/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172594 91177308-0d34-0410-b5e6-96231b3b80d8
* Akira,Jack Carter2013-01-161-0/+16
| | | | | | | | | | | | | | Hope you are feeling better. The Mips RDHWR (Read Hardware Register) instruction was not tested for assembler or dissassembler consumption. This patch adds that functionality. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172579 91177308-0d34-0410-b5e6-96231b3b80d8
* MipsDisassembler.cpp: Prune DecodeHWRegs64RegisterClass() to suppress a ↵NAKAMURA Takumi2013-01-121-16/+0
| | | | | | warning. [-Wunused-function] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172319 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove edis - the enhanced disassembler. Fixes PR14654.Roman Divacky2012-12-191-11/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170578 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the new script to sort the includes of every file under lib.Chandler Carruth2012-12-031-4/+5
| | | | | | | | | | | | | | | | | Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS DSP: add functions which decode DSP and accumulator registers.Akira Hatanaka2012-09-271-0/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164748 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch the fixed-length disassembler to be table-driven.Jim Grosbach2012-08-141-8/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r158846.Akira Hatanaka2012-07-091-114/+77
| | | | | | | | Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
* revert r159851.Akira Hatanaka2012-07-061-17/+67
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159854 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r158846.Akira Hatanaka2012-07-061-67/+17
| | | | | | | Include file MipsGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159851 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r158846.Akira Hatanaka2012-06-201-14/+67
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158855 91177308-0d34-0410-b5e6-96231b3b80d8
* In MipsDisassembler.cpp, instead of defining register class tables, use the onesAkira Hatanaka2012-06-201-67/+14
| | | | | | | | | | | | that are generated by TableGen and are already available in MipsGenRegisterInfo.inc. Suggested by Jakob Stoklund Olesen. Also, fix bug in function DecodeAFGR64RegisterClass. Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158846 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store registers in static tables. Matches other tables.Craig Topper2012-05-241-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157375 91177308-0d34-0410-b5e6-96231b3b80d8
* Move MipsDisassembler classes into an anonymous namespace.Benjamin Kramer2012-05-011-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155915 91177308-0d34-0410-b5e6-96231b3b80d8
* Add disassembler to MIPS. Akira Hatanaka2012-04-171-0/+552
| | | | | | | | Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154935 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r153924. Delete test/MC/Disassembler/Mips and ↵Akira Hatanaka2012-04-031-0/+0
| | | | | | lib/Target/Mips/Disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153926 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r153924. There were buildbot failures.Akira Hatanaka2012-04-031-552/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153925 91177308-0d34-0410-b5e6-96231b3b80d8
* MIPS disassembler support.Akira Hatanaka2012-04-031-0/+552
Patch by Vladimir Medic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153924 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-11-11 11:04:09 +0000