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* Expand pseudos BteqzT8CmpiX16 and BtnezT8CmpiX16.Reed Kotler2013-02-191-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175474 91177308-0d34-0410-b5e6-96231b3b80d8
* Beginning of expanding all current mips16 macro/pseudo instruction sequences.Reed Kotler2013-02-181-1/+3
| | | | | | | | | | | | This expansion will be moved to expandISelPseudos as soon as I can figure out how to do that. There are other instructions which use this ExpandFEXT_T8I816_ins and as soon as I have finished expanding them all, I will delete the macro asm string text so it has no way to be used in the future. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175413 91177308-0d34-0410-b5e6-96231b3b80d8
* One more try to make this look nice. I have lots of pseudo lowering Reed Kotler2013-02-161-0/+3
| | | | | | | | | | as well as 16/32 bit variants to do and so I want this to look nice when I do it. I've been experimenting with this. No new test cases are needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175369 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a different scheme to chose 16/32 variants. This scheme is moreReed Kotler2013-02-161-3/+1
| | | | | | | | | consistent with how BuildMI works. No new tests needed. All should work the same as before. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175342 91177308-0d34-0410-b5e6-96231b3b80d8
* For Mips 16, add the optimization where the 16 bit form of addiu sp can be usedReed Kotler2013-02-131-0/+12
| | | | | | | | | | | | if the offset fits in 11 bits. This makes use of the fact that the abi requires sp to be 8 byte aligned so the actual offset can fit in 8 bits. It will be shifted left and sign extended before being actually used. The assembler or direct object emitter will shift right the 11 bit signed field by 3 bits. We don't need to deal with that here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175073 91177308-0d34-0410-b5e6-96231b3b80d8
* When Mips16 frames grow large, the immediate field may exceed the maximumReed Kotler2013-02-081-5/+7
| | | | | | | | | | allowed size for the instruction. This code uses RegScavenger to fix this. We sometimes need 2 registers for Mips16 so we must handle things differently than how register scavenger is normally used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174696 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] 80 columns.Akira Hatanaka2013-01-041-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171515 91177308-0d34-0410-b5e6-96231b3b80d8
* fix most of remaining issues with large frames.Reed Kotler2012-12-201-0/+27
| | | | | | | | | | | | these patches are tested a lot by test-suite but make check tests are forthcoming once the next few patches that complete this are committed. with the next few patches the pass rate for mips16 is near 100% git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170656 91177308-0d34-0410-b5e6-96231b3b80d8
* Sort includes for all of the .h files under the 'lib' tree. These wereChandler Carruth2012-12-041-1/+1
| | | | | | | | | | missed in the first pass because the script didn't yet handle include guards. Note that the script is now able to handle all of these headers without manual edits. =] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169224 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement ADJCALLSTACKUP and ADJCALLSTACKDOWNReed Kotler2012-10-311-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167107 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo andAkira Hatanaka2012-07-311-0/+5
| | | | | | | | MipsSERegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161092 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definitions of two subclasses of MipsInstrInfo, MipsInstrInfo (for mips16),Akira Hatanaka2012-07-311-0/+71
and MipsSEInstrInfo (for mips32/64). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161081 91177308-0d34-0410-b5e6-96231b3b80d8
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