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* Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce ↵Craig Topper2012-03-052-3/+3
| | | | | | static data size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152016 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store register overlaps to reduce static data.Craig Topper2012-03-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152001 91177308-0d34-0410-b5e6-96231b3b80d8
* Use uint16_t to store registers in callee saved register tables to reduce ↵Craig Topper2012-03-042-2/+2
| | | | | | size of static data. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151996 91177308-0d34-0410-b5e6-96231b3b80d8
* Changes for migrating to using register mask operands.Akira Hatanaka2012-03-016-48/+45
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151847 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix bugs which were introduced when support for base+index floating point loadsAkira Hatanaka2012-03-014-10/+35
| | | | | | | | | | | | | and stores was added. - SelectAddr should return false if Parent is an unaligned f32 load or store. - Only aligned load and store nodes should be matched to select reg+imm floating point instructions. - MIPS does not have support for f64 unaligned load or store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151843 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass endian information to constructors. Define separate functions to createAkira Hatanaka2012-03-015-57/+55
| | | | | | | | | objects for big endian and little endian targets. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151788 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-commit r151623 with fix. Only issue special no-return calls if it's a ↵Evan Cheng2012-02-282-3/+5
| | | | | | direct call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151645 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack ↵Daniel Dunbar2012-02-282-5/+3
| | | | | | prediction. ...", it is breaking the Clang build during the Compiler-RT part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151630 91177308-0d34-0410-b5e6-96231b3b80d8
* remove blanks, and some code formatJia Liu2012-02-2834-156/+156
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151625 91177308-0d34-0410-b5e6-96231b3b80d8
* Some ARM implementaions, e.g. A-series, does return stack prediction. That is,Evan Cheng2012-02-282-3/+5
| | | | | | | | | | | | | | | | | | the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
* Add comments.Akira Hatanaka2012-02-281-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151615 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not reserve $gp as a dedicated global base register if the target ABI is ↵Akira Hatanaka2012-02-281-1/+2
| | | | | | not O32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151614 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for floating point base register + offset register addressing modeAkira Hatanaka2012-02-286-4/+91
| | | | | | | | load and store instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151611 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary template parameters.Akira Hatanaka2012-02-271-15/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151540 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix instruction predicates that were not set correctly.Akira Hatanaka2012-02-271-8/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151538 91177308-0d34-0410-b5e6-96231b3b80d8
* delete useless comment&blankJia Liu2012-02-271-16/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151512 91177308-0d34-0410-b5e6-96231b3b80d8
* Add definitions of floating point multiply add/sub and negative multiplyAkira Hatanaka2012-02-253-8/+71
| | | | | | | | add/sub instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151415 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an option to use a virtual register as the global base register instead ofAkira Hatanaka2012-02-2416-98/+247
| | | | | | | | | | | | | | | | | | | | | | | | | | | reserving a physical register ($gp or $28) for that purpose. This will completely eliminate loads that restore the value of $gp after every function call, if the register allocator assigns a callee-saved register, or eliminate unnecessary loads if it assigns a temporary register. example: .cpload $25 // set $gp. ... .cprestore 16 // store $gp to stack slot 16($sp). ... jalr $25 // function call. clobbers $gp. lw $gp, 16($sp) // not emitted if callee-saved reg is chosen. ... lw $2, 4($gp) ... jalr $25 // function call. lw $gp, 16($sp) // not emitted if $gp is not live after this instruction. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151402 91177308-0d34-0410-b5e6-96231b3b80d8
* comment fixJia Liu2012-02-241-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151341 91177308-0d34-0410-b5e6-96231b3b80d8
* some comment fixJia Liu2012-02-241-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151340 91177308-0d34-0410-b5e6-96231b3b80d8
* replace a balnk with -Jia Liu2012-02-241-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151337 91177308-0d34-0410-b5e6-96231b3b80d8
* 80 columns of Mips InstPrinter MakefileJia Liu2012-02-241-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151332 91177308-0d34-0410-b5e6-96231b3b80d8
* Make all pointers to TargetRegisterClass const since they are all pointers ↵Craig Topper2012-02-221-3/+3
| | | | | | to static data that should not be modified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151134 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a function in MathExtras to do sign extension.Akira Hatanaka2012-02-221-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151107 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead code. Improve llvm_unreachable text. Simplify some control flow.Ahmed Charles2012-02-191-4/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150918 91177308-0d34-0410-b5e6-96231b3b80d8
* remove Emacs-tag form .cpp files in Mips Backend, and fix some typo.Jia Liu2012-02-1727-27/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150805 91177308-0d34-0410-b5e6-96231b3b80d8
* Do not promote i32 arguments to i64. This was causing unnecessary sign extensionAkira Hatanaka2012-02-172-14/+16
| | | | | | | | instructions to be emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150782 91177308-0d34-0410-b5e6-96231b3b80d8
* add Emacs tag and fix some comment error in file headersJia Liu2012-02-1729-28/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150775 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove comment.Akira Hatanaka2012-02-161-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150739 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing whitespace. Add newline.Akira Hatanaka2012-02-161-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150706 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-073-9/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149961 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-051-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
* TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick2012-02-042-8/+5
| | | | | | | | | | Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
* Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick2012-02-032-17/+40
| | | | | | | | | | | Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which isAkira Hatanaka2012-02-034-3/+16
| | | | | | | | | | needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149668 91177308-0d34-0410-b5e6-96231b3b80d8
* Set the correct stack pointer register.Akira Hatanaka2012-02-021-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149585 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer andAkira Hatanaka2012-02-021-2/+4
| | | | | | | | selector registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149584 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DWARF numbers of 64-bit registers.Akira Hatanaka2012-02-021-64/+64
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149583 91177308-0d34-0410-b5e6-96231b3b80d8
* Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM ↵James Molloy2012-01-281-1/+1
| | | | | | | | | | and MIPS ELF backends. Fixes PR11877 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149180 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark 64-bit register RA_64 unused too.Akira Hatanaka2012-01-251-4/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148918 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify MipsFrameLowering::emitPrologue and emitEpilogue.Akira Hatanaka2012-01-251-78/+68
| | | | | | | | | | | | - Use MipsAnalyzeImmediate to expand immediates that do not fit in 16-bit. - Change the types of variables so that they are sufficiently large to handle 64-bit pointers. - Emit instructions to set register $28 in a function prologue after instructions which store callee-saved registers have been emitted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148917 91177308-0d34-0410-b5e6-96231b3b80d8
* Modify MipsRegisterInfo::eliminateFrameIndex to use MipsAnalyzeImmediate toAkira Hatanaka2012-01-251-12/+34
| | | | | | | | | | expand offsets that do not fit in the 16-bit immediate field of load and store instructions. Also change the types of variables so that they are sufficiently large to handle 64-bit pointers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148916 91177308-0d34-0410-b5e6-96231b3b80d8
* MipsAnalyzeImmediate.h: Fix to add DataTypes.h for msvc.NAKAMURA Takumi2012-01-251-0/+1
| | | | | | inttypes.h is not supplied in msvc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148912 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/Mips: Unbreak CMake build.NAKAMURA Takumi2012-01-251-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148909 91177308-0d34-0410-b5e6-96231b3b80d8
* Lower 64-bit immediates using MipsAnalyzeImmediate that has just been added. Akira Hatanaka2012-01-252-31/+42
| | | | | | | | Add a test case to show fewer instructions are needed to load an immediate with the new way of loading immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148908 91177308-0d34-0410-b5e6-96231b3b80d8
* Add class MipsAnalyzeImmediate which comes up with an instruction sequence toAkira Hatanaka2012-01-252-0/+215
| | | | | | | | load an immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148900 91177308-0d34-0410-b5e6-96231b3b80d8
* Sign-extend 32-bit integer arguments when they are passed in 64-bit registers,Akira Hatanaka2012-01-241-1/+4
| | | | | | | | which is what N32/64 does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148875 91177308-0d34-0410-b5e6-96231b3b80d8
* Pass CCState by reference.Akira Hatanaka2012-01-241-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148871 91177308-0d34-0410-b5e6-96231b3b80d8
* Pattern for f32 to i64 conversion.Akira Hatanaka2012-01-241-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148869 91177308-0d34-0410-b5e6-96231b3b80d8
* 64-bit sign extension in register instructions.Akira Hatanaka2012-01-242-5/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148862 91177308-0d34-0410-b5e6-96231b3b80d8
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