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* Compile this:Chris Lattner2006-03-011-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | void foo(float a, int *b) { *b = a; } to this: _foo: fctiwz f0, f1 stfiwx f0, 0, r4 blr instead of this: _foo: fctiwz f0, f1 stfd f0, -8(r1) lwz r2, -4(r1) stw r2, 0(r4) blr This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the right thing for GCC bugzilla 26505. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26447 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll.Chris Lattner2006-03-011-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26445 91177308-0d34-0410-b5e6-96231b3b80d8
* split register class handling from explicit physreg handling.Chris Lattner2006-02-221-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26308 91177308-0d34-0410-b5e6-96231b3b80d8
* Updates to match change of getRegForInlineAsmConstraint prototypeChris Lattner2006-02-211-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26305 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement getConstraintType for PPC.Chris Lattner2006-02-071-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26042 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the simple PPC integer constraintsChris Lattner2006-02-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26027 91177308-0d34-0410-b5e6-96231b3b80d8
* add info about the inline asm register constraints for PPCChris Lattner2006-01-311-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25853 91177308-0d34-0410-b5e6-96231b3b80d8
* Use PPCISD::CALL instead of ISD::CALLChris Lattner2006-01-271-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25717 91177308-0d34-0410-b5e6-96231b3b80d8
* Make llvm.frame/returnaddr not crash on ppcChris Lattner2006-01-271-4/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25710 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET forNate Begeman2006-01-271-3/+0
| | | | | | | | the same functionality. This addresses another piece of bug 680. Next, on to fixing Alpha VAARG, which I broke last time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25696 91177308-0d34-0410-b5e6-96231b3b80d8
* First part of bug 680:Nate Begeman2006-01-251-7/+0
| | | | | | | | Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same way as everything else. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25606 91177308-0d34-0410-b5e6-96231b3b80d8
* Give PPCISD:: nodes legible names in dumps.Chris Lattner2006-01-091-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25166 91177308-0d34-0410-b5e6-96231b3b80d8
* Pattern-match return. Includes gross hack!Nate Begeman2005-12-201-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24874 91177308-0d34-0410-b5e6-96231b3b80d8
* Prepare support for AltiVec multiply, divide, and sqrt.Nate Begeman2005-12-131-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24700 91177308-0d34-0410-b5e6-96231b3b80d8
* Use new PPC-specific nodes to represent shifts which require the 6-bitChris Lattner2005-12-061-0/+6
| | | | | | | | | | amount handling that PPC provides. These are generated by the lowering code and prevents the dag combiner from assuming (rightfully) that the shifts don't only look at 5 bits. This fixes a miscompilation of crafty with the new front-end. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24615 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an initial hack at legalizing GlobalAddress into the appropriate nodesChris Lattner2005-11-171-0/+11
| | | | | | | | | | | | | | | | | on Darwin to remove smarts from the isel. This is currently disabled by default (uncomment setOperationAction(ISD::GlobalAddress to enable it). tblgen needs to become smarter about tglobaladdr nodes and bigger patterns needed to be added to the .td file. However, we can currently emit stuff like this: :) li r2, lo16(L_x$non_lazy_ptr) lis r3, ha16(L_x$non_lazy_ptr) lwzx r2, r3, r2 The obvious improvements will follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24390 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the ability to lower return instructions to TargetLowering. ThisNate Begeman2005-10-181-0/+3
| | | | | | | | allows us to lower legal return types to something else, to meet ABI requirements (such as that i64 be returned in two i32 regs on Darwin/ppc). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23802 91177308-0d34-0410-b5e6-96231b3b80d8
* More PPC32 -> PPC changes, as well as merging some classes that wereNate Begeman2005-10-161-3/+3
| | | | | | | redundant after the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename PowerPC*.h to PPC*.hChris Lattner2005-10-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when weNate Begeman2005-09-061-3/+9
| | | | | | | | | | are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts, such as the PowerPC 970. This speeds up 189.lucas from 81.99 to 32.64 seconds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23250 91177308-0d34-0410-b5e6-96231b3b80d8
* Move FCTIWZ handling out of the instruction selectors and into legalization,Chris Lattner2005-08-311-0/+4
| | | | | | | getting them out of the business of making stack slots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23180 91177308-0d34-0410-b5e6-96231b3b80d8
* implement SELECT_CC fully for the DAG->DAG isel!Chris Lattner2005-08-261-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23101 91177308-0d34-0410-b5e6-96231b3b80d8
* Make fsel emission work with both the pattern and dag-dag selectors, byChris Lattner2005-08-261-1/+14
| | | | | | | | | giving it a non-instruction opcode. The dag->dag selector used to not select the operands of the fsel, because it thought that whole tree was already selected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23091 91177308-0d34-0410-b5e6-96231b3b80d8
* add initial support for converting select_cc -> fsel in the legalizerChris Lattner2005-08-261-0/+4
| | | | | | | | | | instead of in the backend. This currently handles fsel cases with registers, but doesn't have the 0.0 and -0.0 optimization enabled yet. Once this is finished, special hack for fp immediates can go away. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23075 91177308-0d34-0410-b5e6-96231b3b80d8
* Pull the LLVM -> DAG lowering code out of the pattern selector so that itChris Lattner2005-08-161-0/+53
can be shared with the DAG->DAG selector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22799 91177308-0d34-0410-b5e6-96231b3b80d8
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