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* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-061-5/+1
| | | | | | | | | | | | instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45654 91177308-0d34-0410-b5e6-96231b3b80d8
* remove some isStore flags that are now inferred automatically.Chris Lattner2008-01-061-2/+2
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* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
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* Temporary solution: added a different set of BCTRL_Macho / BCTRL_ELF with ↵Evan Cheng2007-10-231-3/+9
| | | | | | right callee-saved defs set for ppc64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43248 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-111-2/+2
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* Fix for PR1613: added 64-bit rotate left PPC instructions and patterns.Evan Cheng2007-09-041-0/+10
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* Some out operands were incorrectly specified as input operands.Evan Cheng2007-08-011-9/+9
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* No more noResults.Evan Cheng2007-07-211-4/+4
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* Oops. These stores actually produce results.Evan Cheng2007-07-201-4/+4
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* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-99/+103
| | | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for 128-bit add/sub on ppc64Chris Lattner2007-05-171-0/+34
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* The PPC64 ELF ABI is "intended to use the same structure layout and calling ↵Nicolas Geoffray2007-04-031-2/+3
| | | | | | | | | | convention rules as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/). Change all ELF tests to ELF32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35624 91177308-0d34-0410-b5e6-96231b3b80d8
* The ELF ABI specifies F1-F8 registers as argument registers for double, notNicolas Geoffray2007-04-031-1/+1
| | | | | | | F1-F10. This affects only ELF, not MachO. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35622 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix CodeGen/PowerPC/2007-03-24-cntlzd.llChris Lattner2007-03-251-1/+4
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* Differentiate between the MachO and the ELF ABI the CALL instruction.Nicolas Geoffray2007-02-271-3/+2
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* one important bugfix: PPC32 didn't have both elf and macho support forChris Lattner2007-02-251-3/+3
| | | | | | | | | | external symbols and global addresses. Add the missing ones. one important workaround: PPCISD::CALL is matched by both PPCcall_ELF and PPCcall_Macho, disable the _ELF patterns for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34601 91177308-0d34-0410-b5e6-96231b3b80d8
* implement support for the linux/ppc function call ABI. Patch byChris Lattner2007-02-251-8/+36
| | | | | | | Nicolas Geoffray! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34574 91177308-0d34-0410-b5e6-96231b3b80d8
* Patterns no longer needed due to fix in the DAG combiner.Jim Laskey2006-12-151-4/+0
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* Not all test cases are created equal. This fix is needed.Jim Laskey2006-12-151-0/+4
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* Not needed. Misinterpreted error message from other bug (Missing load/storeJim Laskey2006-12-151-4/+0
| | | | | | | relocations.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32604 91177308-0d34-0410-b5e6-96231b3b80d8
* Provide 64-bit support for i64 sextload<i8>.Jim Laskey2006-12-151-0/+4
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* Reduce number of instructions to load 64-bit constants.Jim Laskey2006-12-121-42/+0
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* implement sextinreg i8->i64 and i16->i64Chris Lattner2006-12-061-0/+8
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* This is a general clean up of the PowerPC ABI. Address several problems andJim Laskey2006-11-161-0/+6
| | | | | | | | | | bugs including making sure that the TOS links back to the previous frame, that the maximum call frame size is not included twice when using frame pointers, no longer growing the frame on calls, double storing of SP and a cleaner/faster dynamic alloca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31792 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a regression that I introduced. stdu should scale the offset by 4Chris Lattner2006-11-161-1/+1
| | | | | | | before printing it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31791 91177308-0d34-0410-b5e6-96231b3b80d8
* add ppc64 r+i stores with update.Chris Lattner2006-11-161-26/+59
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* Stop using isTwoAddress, switching to operand constraints instead.Chris Lattner2006-11-151-12/+17
| | | | | | | | | Tell the codegen emitter that specific operands are not to be encoded, fixing JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate even when general preinc loads are not enabled). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31770 91177308-0d34-0410-b5e6-96231b3b80d8
* fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memriChris Lattner2006-11-151-16/+12
| | | | | | | addrmodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31757 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the PPC regressions last nightChris Lattner2006-11-151-1/+1
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* Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 callsChris Lattner2006-11-141-1/+42
| | | | | | | | | clobber. This allows LR8 to be save/restored correctly as a 64-bit quantity, instead of handling it as a 32-bit quantity. This unbreaks ppc64 codegen when the code is actually located above the 4G boundary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31734 91177308-0d34-0410-b5e6-96231b3b80d8
* implement proper PPC64 prolog/epilog codegen.Chris Lattner2006-11-111-0/+5
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* Mark operands as symbol lo instead of imm32 so that they print lo(x) aroundChris Lattner2006-11-111-5/+5
| | | | | | | globals. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31672 91177308-0d34-0410-b5e6-96231b3b80d8
* implement preinc support for r+i loads on ppc64Chris Lattner2006-11-101-4/+38
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* Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng2006-10-131-6/+6
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* Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng2006-10-091-20/+20
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* Shift amounts are always 32-bits, even in 64-bit mode. This fixesChris Lattner2006-09-281-6/+6
| | | | | | | CodeGen/PowerPC/2006-09-28-shift_64.ll git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30652 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the implicit def instructions look like other instrs.Chris Lattner2006-07-181-1/+1
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* Add missing PPC64 extload/truncstoresChris Lattner2006-07-141-7/+83
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* Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :)Chris Lattner2006-06-271-2/+0
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* Add a pattern for i64 sra. Print 8-byte units with a space between the .quadChris Lattner2006-06-271-2/+4
| | | | | | | and the data git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28934 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 64-bit MTCTR so that indirect calls work.Chris Lattner2006-06-271-0/+4
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* Fix an incorrect store pattern. This fixes em3d.Chris Lattner2006-06-271-1/+1
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* Implement 64-bit undef, sub, shl/shr, srem/uremChris Lattner2006-06-271-3/+16
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* Add zextload from i32 -> i64, with this, perimeter works.Chris Lattner2006-06-271-0/+3
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* Rearrange compares, add ADDI8, add sext from 32-to-64 bit registerChris Lattner2006-06-261-8/+20
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* Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit fileChris Lattner2006-06-201-11/+22
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* add some logical opsChris Lattner2006-06-201-3/+28
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* Add some more immediate patterns. This allows us to compile:Chris Lattner2006-06-201-0/+30
| | | | | | | | | | | | | | | | | | | | | void test6() { Y = 0xABCD0123BCDE4567; } into: _test6: lis r2, -21555 lis r3, ha16(_Y) ori r2, r2, 291 rldicr r2, r2, 32, 31 oris r2, r2, 48350 ori r2, r2, 17767 std r2, lo16(_Y)(r3) blr git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28885 91177308-0d34-0410-b5e6-96231b3b80d8
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