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* Change the "enable/disable" mechanism so that we can enable PPC registerBill Wendling2008-03-101-46/+51
| | | | | | | scavenging for 32-bit and 64-bit separately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48186 91177308-0d34-0410-b5e6-96231b3b80d8
* fix 80 col violations.Chris Lattner2008-03-101-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48166 91177308-0d34-0410-b5e6-96231b3b80d8
* Stylistic modifications. No functionality changes.Nicolas Geoffray2008-03-101-44/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48158 91177308-0d34-0410-b5e6-96231b3b80d8
* Add description of individual bits in CR. This fix PR1765.Nicolas Geoffray2008-03-101-0/+56
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48143 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a command-line option to turn register scavenging on/off for PPC.Bill Wendling2008-03-041-7/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47915 91177308-0d34-0410-b5e6-96231b3b80d8
* This is the initial check-in for adding register scavenging to PPC. (Currently,Bill Wendling2008-03-031-31/+54
| | | | | | | | | | | PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that it uses a register other than the default R0 register (the scavenger scrounges for one). A significant part of this patch fixes how kill information is handled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47863 91177308-0d34-0410-b5e6-96231b3b80d8
* commuteInstr() can now commute non-ssa machine instrs.Evan Cheng2008-02-131-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47043 91177308-0d34-0410-b5e6-96231b3b80d8
* It's not always safe to fold movsd into xorpd, etc. Check the alignment of ↵Evan Cheng2008-02-081-2/+3
| | | | | | the load address first to make sure it's 16 byte aligned. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46893 91177308-0d34-0410-b5e6-96231b3b80d8
* remove MachineOpCode typedef.Chris Lattner2008-01-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45679 91177308-0d34-0410-b5e6-96231b3b80d8
* Move even more functionality from MRegisterInfo into TargetInstrInfo.Owen Anderson2008-01-071-0/+79
| | | | | | | Some day I'll get it all moved over... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45672 91177308-0d34-0410-b5e6-96231b3b80d8
* Move some more instruction creation methods from RegisterInfo into InstrInfo.Owen Anderson2008-01-011-0/+230
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45484 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug in my previous patch: refer to the impl not the pure virtual ↵Chris Lattner2008-01-011-1/+1
| | | | | | version. It's unclear why gcc would ever compile this... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45476 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a problem where lib/Target/TargetInstrInfo.h would include and useChris Lattner2008-01-011-1/+1
| | | | | | | | | | | a header file from libcodegen. This violates a layering order: codegen depends on target, not the other way around. The fix to this is to split TII into two classes, TII and TargetInstrInfoImpl, which defines stuff that depends on libcodegen. It is defined in libcodegen, where the base is not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8
* Move copyRegToReg from MRegisterInfo to TargetInstrInfo. This is part of theOwen Anderson2007-12-311-0/+28
| | | | | | | Machine-level API cleanup instigated by Chris. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45470 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new shorter predicates for testing machine operands for various types: Chris Lattner2007-12-301-11/+11
| | | | | | | | | | | | | | e.g. MO.isMBB() instead of MO.isMachineBasicBlock(). I don't plan on switching everything over, so new clients should just start using the shorter names. Remove old long accessors, switching everything over to use the short accessor: getMachineBasicBlock() -> getMBB(), getConstantPoolIndex() -> getIndex(), setMachineBasicBlock -> setMBB(), etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45464 91177308-0d34-0410-b5e6-96231b3b80d8
* More cleanups for MachineOperand:Chris Lattner2007-12-301-8/+2
| | | | | | | | | | | - Eliminate the static "print" method for operands, moving it into MachineOperand::print. - Change various set* methods for register flags to take a bool for the value to set it to. Remove unset* methods. - Group methods more logically by operand flavor in MachineOperand.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45461 91177308-0d34-0410-b5e6-96231b3b80d8
* Use MachineOperand::getImm instead of MachineOperand::getImmedValue. ↵Chris Lattner2007-12-301-9/+9
| | | | | | Likewise setImmedValue -> setImm git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45453 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* Add lengthof and endof templates that hide a lot of sizeof computations.Owen Anderson2007-09-071-1/+2
| | | | | | | Patch by Sterling Stein! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41758 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle blocks with 2 unconditional branches in AnalyzeBranch.Dale Johannesen2007-06-131-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37571 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a utility routine to check for unpredicated terminator instruction.Evan Cheng2007-06-081-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37528 91177308-0d34-0410-b5e6-96231b3b80d8
* BlockHasNoFallThrough() now returns true if block ends with a return ↵Evan Cheng2007-05-211-0/+1
| | | | | | instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37266 91177308-0d34-0410-b5e6-96231b3b80d8
* RemoveBranch() and InsertBranch() now returns number of instructions deleted ↵Evan Cheng2007-05-181-9/+12
| | | | | | / inserted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37192 91177308-0d34-0410-b5e6-96231b3b80d8
* Relex assertions to account for additional implicit def / use operands.Evan Cheng2007-04-251-5/+5
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* What should be the last unnecessary <iostream>s in the library.Bill Wendling2006-12-071-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
* Change MachineInstr ctor's to take a TargetInstrDescriptor reference insteadEvan Cheng2006-11-271-5/+5
| | | | | | | of opcode and number of operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
* convert PPC::BCC to use the 'pred' operand instead of separate predicateChris Lattner2006-11-171-3/+3
| | | | | | | | | value and CR reg #. This requires swapping the order of these everywhere that touches BCC and requires us to write custom matching logic for PPCcondbranch :( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31835 91177308-0d34-0410-b5e6-96231b3b80d8
* rename PPC::COND_BRANCH to PPC::BCCChris Lattner2006-11-171-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31834 91177308-0d34-0410-b5e6-96231b3b80d8
* start using PPC predicates more consistently.Chris Lattner2006-11-171-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31833 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly transfer kill / dead info.Evan Cheng2006-11-151-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31765 91177308-0d34-0410-b5e6-96231b3b80d8
* Matches MachineInstr changes.Evan Cheng2006-11-131-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31712 91177308-0d34-0410-b5e6-96231b3b80d8
* implement the BlockHasNoFallThrough hookChris Lattner2006-10-281-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31264 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement support for branch reversal, fix a bug in branch analysis.Chris Lattner2006-10-211-2/+5
| | | | | | | | | | | | | | | | | This provides stuff like: cmpw cr0, r15, r29 mr r14, r15 - bge cr0, LBB3_111 ;bb656 - b LBB3_90 ;bb501 + blt cr0, LBB3_90 ;bb501 LBB3_111: ;bb656 lwz r18, 68(r1) which is particularly good for dispatch group formation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31101 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify code, no functionality changeChris Lattner2006-10-211-4/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31097 91177308-0d34-0410-b5e6-96231b3b80d8
* implement support for inserting a cond branchChris Lattner2006-10-211-4/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31096 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for inserting an uncond branchChris Lattner2006-10-171-2/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31003 91177308-0d34-0410-b5e6-96231b3b80d8
* implement branch inspection/modification methods.Chris Lattner2006-10-131-0/+93
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30946 91177308-0d34-0410-b5e6-96231b3b80d8
* In 64-bit mode, 64-bit GPRs are callee saved, not 32-bit ones.Chris Lattner2006-07-111-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29096 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit fileChris Lattner2006-06-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28889 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the getPointerRegClass method, which is required for the ptr_rcChris Lattner2006-06-171-3/+13
| | | | | | | magic to work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28847 91177308-0d34-0410-b5e6-96231b3b80d8
* Move some methods out of MachineInstr into MachineOperandChris Lattner2006-05-041-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8
* teach the ppc backend how to spill/reload vector regsChris Lattner2006-03-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26806 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for copying registers. still needed: spilling and reloading themChris Lattner2006-03-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26800 91177308-0d34-0410-b5e6-96231b3b80d8
* implement TII::insertNoopChris Lattner2006-03-051-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26562 91177308-0d34-0410-b5e6-96231b3b80d8
* add 64b gpr store to the possible list of isStoreToStackSlot opcodes.Nate Begeman2006-02-021-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25916 91177308-0d34-0410-b5e6-96231b3b80d8
* implement isStoreToStackSlot for PPCChris Lattner2006-02-021-1/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25914 91177308-0d34-0410-b5e6-96231b3b80d8
* Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far ↵Chris Lattner2006-02-021-0/+19
| | | | | | more logical place. Other methods should also be moved if anyoneis interested. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
* teach ppc backend these are copiesChris Lattner2005-10-191-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23813 91177308-0d34-0410-b5e6-96231b3b80d8
* First bits of 64 bit PowerPC stuff, currently disabled. A lot of this isNate Begeman2005-10-181-1/+1
| | | | | | | purely mechanical. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8
* More PPC32 -> PPC changes, as well as merging some classes that wereNate Begeman2005-10-161-6/+6
| | | | | | | redundant after the change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
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