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* Add PPC 440 scheduler and some associated testsHal Finkel2011-10-171-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142170 91177308-0d34-0410-b5e6-96231b3b80d8
* Set CR1EQ only when lowering vararg floating arguments (not any varargRoman Divacky2011-08-301-0/+4
| | | | | | | arguments as before), unset CR1EQ otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138802 91177308-0d34-0410-b5e6-96231b3b80d8
* Code generation for 'fence' instruction.Eli Friedman2011-07-271-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136283 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointlessCameron Zwarich2011-05-191-2/+1
| | | | | | | | piclabel operand. The operand in the tablegen definition doesn't actually turn into an MI operand, so it just confuses anything checking the TargetInstrDesc for the number of operands. It suffices to just have an implicit def of LR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131626 91177308-0d34-0410-b5e6-96231b3b80d8
* PowerPC atomic pseudos clobber CR0, they don't read it.Jakob Stoklund Olesen2011-04-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128829 91177308-0d34-0410-b5e6-96231b3b80d8
* Flag -> Glue, the ongoing sagaChris Lattner2010-12-231-20/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122513 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug I introduced in the ppc refactoring, which caused longChris Lattner2010-11-161-0/+1
| | | | | | | | | | | | branches to be emitted as: bne cr0, 2 instead of: bne cr0, $+8 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119317 91177308-0d34-0410-b5e6-96231b3b80d8
* split out an encoder for memri operands, allowing a relocation to be ploppedChris Lattner2010-11-151-5/+6
| | | | | | | | | | | | | | | | | | into the immediate field. This allows us to encode stuff like this: lbz r3, lo16(__ZL4init)(r4) ; globalopt.cpp:5 ; encoding: [0x88,0x64,A,A] ; fixup A - offset: 0, value: lo16(__ZL4init), kind: fixup_ppc_lo16 stw r3, lo16(__ZL1s)(r5) ; globalopt.cpp:6 ; encoding: [0x90,0x65,A,A] ; fixup A - offset: 0, value: lo16(__ZL1s), kind: fixup_ppc_lo16 With this, we should have a completely function MCCodeEmitter for PPC, wewt. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119134 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for encoding the lo14 forms used for a few PPC64 addressingChris Lattner2010-11-151-0/+1
| | | | | | | | | | | modes. For example, we now get: ld r3, lo16(_G)(r3) ; encoding: [0xe8,0x63,A,0bAAAAAA00] ; fixup A - offset: 0, value: lo16(_G), kind: fixup_ppc_lo14 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119133 91177308-0d34-0410-b5e6-96231b3b80d8
* implement the start of support for lo16 and ha16, allowing us to get stuff like:Chris Lattner2010-11-151-0/+2
| | | | | | | | lis r4, ha16(__ZL4init) ; encoding: [0x3c,0x80,A,A] ; fixup A - offset: 0, value: ha16(__ZL4init), kind: fixup_ppc_ha16 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119127 91177308-0d34-0410-b5e6-96231b3b80d8
* change direct branches to encode with the same encoding methodChris Lattner2010-11-151-4/+8
| | | | | | | | | as direct calls. Change conditional branches to encode with their own method, simplifying the JIT encoder and making room for adding an mc fixup. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119125 91177308-0d34-0410-b5e6-96231b3b80d8
* eliminate a now-unneeded operand printer.Chris Lattner2010-11-151-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119124 91177308-0d34-0410-b5e6-96231b3b80d8
* split call operands out to their own encoding class, simplifyingChris Lattner2010-11-151-0/+1
| | | | | | | | | | | code in the JIT. Use this to form the first fixup for the PPC backend, giving us stuff like this: bl L_foo$stub ; encoding: [0b010010AA,A,A,0bAAAAAA01] ; fixup A - offset: 0, value: L_foo$stub, kind: fixup_ppc_br24 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119123 91177308-0d34-0410-b5e6-96231b3b80d8
* add proper encoding for MTCRF instead of using a hack.Chris Lattner2010-11-151-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119121 91177308-0d34-0410-b5e6-96231b3b80d8
* add basic encoding support for immediates and registers, allowing us Chris Lattner2010-11-151-4/+1
| | | | | | | | | | | | to encode all of these instructions correctly (for example): mflr r0 ; encoding: [0x7c,0x08,0x02,0xa6] stw r0, 8(r1) ; encoding: [0x90,0x01,0x00,0x08] stwu r1, -64(r1) ; encoding: [0x94,0x21,0xff,0xc0] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119118 91177308-0d34-0410-b5e6-96231b3b80d8
* remove asmstrings (which can never be printed) from pseudo Chris Lattner2010-11-151-62/+35
| | | | | | | | instructions, allowing is to eliminate some dead operand printing methods from the instprinter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119113 91177308-0d34-0410-b5e6-96231b3b80d8
* lower PPC::MFCRpseud when transforming to MC, avoiding callingChris Lattner2010-11-141-0/+7
| | | | | | | the aborting printSpecial() method. This gets us to 8 failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119084 91177308-0d34-0410-b5e6-96231b3b80d8
* Emit COPY instead of FMR/FMSD instructions for floating point conversion onJakob Stoklund Olesen2010-07-161-11/+8
| | | | | | PowerPC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108555 91177308-0d34-0410-b5e6-96231b3b80d8
* The PPC MFCR instruction implicitly uses all 8 of the CRDale Johannesen2010-05-201-6/+9
| | | | | | | | | | | | | | | | registers. Currently it is not so marked, which leads to VCMPEQ instructions that feed into it getting deleted. If it is so marked, local RA complains about this sequence: vreg = MCRF CR0 MFCR <kill of whatever preg got assigned to vreg> All current uses of this instruction are only interested in one of the 8 CR registers, so redefine MFCR to be a normal unary instruction with a CR input (which is emitted only as a comment). That avoids all problems. 7739628. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104238 91177308-0d34-0410-b5e6-96231b3b80d8
* Set isTerminator on TRAP instructions.Dan Gohman2010-05-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103778 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use isBarrier for the PowerPC sync instruction. isBarrier is forDan Gohman2010-05-141-1/+0
| | | | | | | control barriers, not memory ordering barriers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103777 91177308-0d34-0410-b5e6-96231b3b80d8
* set SDNPVariadic on nodes throughout the rest of the targets thatChris Lattner2010-03-191-6/+10
| | | | | | | need them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98937 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge PPC instructions FMRS and FMRD into a single FMR instruction.Jakob Stoklund Olesen2010-02-261-9/+5
| | | | | | | | | This is possible because F8RC is a subclass of F4RC. We keep FMRSD around so fextend has a pattern. Also allow folding of memory operands on FMRSD. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97275 91177308-0d34-0410-b5e6-96231b3b80d8
* remove a bunch of dead named arguments in input patterns,Chris Lattner2010-02-231-5/+5
| | | | | | | though some look dubious afaict, these are all ok. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96899 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate some uses of immAllOnes, just use -1, it doesChris Lattner2010-02-211-2/+2
| | | | | | | the same thing and is more efficient for the matcher. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96712 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't specify CR sub-registers as implicit defs of BL instructions.Jakob Stoklund Olesen2010-01-051-6/+2
| | | | | | | It is enough to give the super registers CR0, CR1, ..., and specifying the sub-registers as well causes confusion in the liveness computations. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92778 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for calls through function pointers in the 64-bit PowerPC SVR4 ABI.Tilmann Scheller2009-12-181-0/+6
| | | | | | Patch contributed by Ken Werner of IBM! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91680 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove ISD::DEBUG_LOC and ISD::DBG_LABEL, which are no longer used.Dan Gohman2009-11-231-9/+0
| | | | | | | | | Note that "hasDotLocAndDotFile"-style debug info was already broken; people wanting this functionality should implement it in the AsmPrinter/DwarfWriter code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89711 91177308-0d34-0410-b5e6-96231b3b80d8
* Add PowerPC codegen for indirect branches.Bob Wilson2009-11-041-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86050 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-291-4/+4
| | | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-8/+8
| | | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82794 91177308-0d34-0410-b5e6-96231b3b80d8
* Model the carry bit on ppc32. Without this we couldDale Johannesen2009-09-181-11/+25
| | | | | | | | | move a SUBFC (etc.) below the SUBFE (etc.) that consumed the carry bit. Add missing ADDIC8, noticed along the way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82266 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the PowerPC 64-bit SVR4 ABI.Tilmann Scheller2009-08-151-0/+8
| | | | | | | | | | | | | | | | | | The Link Register is volatile when using the 32-bit SVR4 ABI. Make it possible to use the 64-bit SVR4 ABI. Add non-volatile registers for the 64-bit SVR4 ABI. Make sure r2 is a reserved register when using the 64-bit SVR4 ABI. Update PPCFrameInfo for the 64-bit SVR4 ABI. Add FIXME for 64-bit Darwin PPC. Insert NOP instruction after direct function calls. Emit official procedure descriptors. Create TOC entries for GlobalAddress references. Spill 64-bit non-volatile registers to the correct slots. Only custom lower VAARG when using the 32-bit SVR4 ABI. Use simple VASTART lowering for the 64-bit SVR4 ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79091 91177308-0d34-0410-b5e6-96231b3b80d8
* Split EVT into MVT and EVT, the former representing _just_ a primitive type, ↵Owen Anderson2009-08-111-3/+3
| | | | | | | | | while the latter is capable of representing either a primitive or an extended type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename MVT to EVT, in preparation for splitting SimpleValueType out into its ↵Owen Anderson2009-08-101-3/+3
| | | | | | own struct type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
* Major calling convention code refactoring.Dan Gohman2009-08-051-3/+0
| | | | | | | | | | | | | | | | | | | | Instead of awkwardly encoding calling-convention information with ISD::CALL, ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering provides three virtual functions for targets to override: LowerFormalArguments, LowerCall, and LowerRet, which replace the custom lowering done on the special nodes. They provide the same information, but in a more immediately usable format. This also reworks much of the target-independent tail call logic. The decision of whether or not to perform a tail call is now cleanly split between target-independent portions, and the target dependent portion in IsEligibleForTailCallOptimization. This also synchronizes all in-tree targets, to help enable future refactoring and feature work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78142 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor ABI code in the PowerPC backend.Tilmann Scheller2009-07-031-33/+33
| | | | | | | | | | | | Make CalculateParameterAndLinkageAreaSize() Darwin-specific. Remove SVR4 specific code from LowerCALL_Darwin() and LowerFORMAL_ARGUMENTS_Darwin(). Rename MachoABI to DarwinABI for consistency. Rename ELF ABI to SVR4 ABI for consistency. Factor out common call return lowering between the Darwin and SVR4 ABI. Factor out common call lowering between the Darwin and SVR4 ABI. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74766 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the SVR4 ABI for PowerPC.Tilmann Scheller2009-07-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | Implement LowerFORMAL_ARGUMENTS_SVR4(). Implement LowerCALL_SVR4(). Add support for split arguments. Implement by value parameter passing for aggregates. Add support for variable argument lists. Create the spill area for argument registers of variable argument functions no longer at a fixed offset. Make sure callee saved registers are spilled to the correct stack offsets. Change allocation order of non-volatile floating-point registers. Add VRSAVE to the list of callee-saved registers, add CallConvLowering for vararg calls. Add support for variable argument calls with Vector arguments. Add support for VR and VRSAVE save area, improve allocation order for non-volatile vector registers. Stop creating illegal i8 values in LowerVASTART(). Add memory access width hints. Make sure to reserve space on the stack for the frame pointer. When using the SVR4 ABI, reserve r13 for the Small Data Area pointer. Assure that the frame pointer is spilled to the correct location on the stack. Some FP registers were not marked as volatile. Make sure the i64 words from a long double are passed either both in registers or both on the stack. Only put integer arguments in registers which are not marked with the inreg flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74765 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.Dan Gohman2008-12-031-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a sanity-check to tablegen to catch the case where isSimpleLoadDan Gohman2008-12-031-0/+2
| | | | | | | | | | is set but mayLoad is not set. Fix all the problems this turned up. Change code to not use isSimpleLoad instead of mayLoad unless it really wants isSimpleLoad. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60459 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a RM pseudoreg for the rounding mode, whichDale Johannesen2008-10-291-143/+163
| | | | | | | | | | | | | | | | | | | allows ppcf128->int conversion to work with DeadInstructionElimination. This is now turned off but RM is harmless. It does not do a complete job of modeling the rounding mode. Revert marking MFCR as using all 7 CR subregisters; while correct, this caused the problem in PR 2964, plus the local RA crash noted in the comments. This was needed to make DeadInstructionElimination, but as we are not running that, it is backed out for now. Eventually it should go back in and the other problems fixed where they're broken. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58391 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark MFCR as reading all condition code registers.Dale Johannesen2008-10-241-0/+2
| | | | | | | | | Prevents some more overzealous deletions (mostly in AltiVec code). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58121 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark defs and uses of CTR and LR correctly.Dale Johannesen2008-10-231-6/+16
| | | | | | | | | | Prevents DeadMachineInstructionElim from thinking things like MTCTR are dead (fixes massive testsuite breakage at -O0). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58043 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix warnings about mb/me being potentially usedDuncan Sands2008-10-161-2/+2
| | | | | | | uninitialized in these functions with gcc-4.3. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57635 91177308-0d34-0410-b5e6-96231b3b80d8
* Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's asChris Lattner2008-10-111-2/+2
| | | | | | | | | parameters instead of raw Constants. This prevents the constants from being selected by the isel pass, fixing PR2735. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57385 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename ConstantSDNode::getValue to getZExtValue, for consistencyDan Gohman2008-09-121-14/+14
| | | | | | | | with ConstantInt. This led to fixing a bug in TargetLowering.cpp using getValue instead of getAPIntValue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement partial-word binary atomics on ppc.Dale Johannesen2008-08-281-0/+66
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55478 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement 32 & 64 bit versions of PPC atomicDale Johannesen2008-08-251-0/+22
| | | | | | | | binary primitives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55343 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove PPC-specific lowering for atomics; theDale Johannesen2008-08-251-29/+6
| | | | | | | | | | generic stuff works fine. Mark rewritten cmp-and-swap as not using CR1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55336 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement __sync_synchronize on ppc32. Patch by Gary Benson.Dale Johannesen2008-08-221-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55186 91177308-0d34-0410-b5e6-96231b3b80d8
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