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* R600: Fix selection failure on EXTLOADMatt Arsenault2013-11-131-1/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194547 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Reenable llvm.R600.load.input/interp.input for compatibilityVincent Lejeune2013-11-122-0/+47
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194484 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-122-2/+64
| | | | | | | | | | | | | | | | | | | | | | | Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194443 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-114-41/+39
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194425 91177308-0d34-0410-b5e6-96231b3b80d8
* Make method staticMatt Arsenault2013-11-102-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194340 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix missing C++ mode commentMatt Arsenault2013-11-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194339 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix LowerUDIVREMVincent Lejeune2013-11-061-5/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194153 91177308-0d34-0410-b5e6-96231b3b80d8
* Use isa<> instead of dyn_cast<> with unused valueMatt Arsenault2013-11-011-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193869 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove another unused flag.Rafael Espindola2013-10-311-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193756 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused flag.Rafael Espindola2013-10-311-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193752 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a few typosMatt Arsenault2013-10-301-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193723 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Custom lower f32 = uint_to_fp i64Tom Stellard2013-10-302-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193701 91177308-0d34-0410-b5e6-96231b3b80d8
* Removing a switch statement that contains only a default label. This ↵Aaron Ballman2013-10-291-28/+25
| | | | | | resolves an MSVC warning. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193649 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add compute support for CI v2Tom Stellard2013-10-296-9/+24
| | | | | | | | | v2: - Fix LDS size calculation Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193621 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Expand vector FSQRT opsTom Stellard2013-10-291-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193620 91177308-0d34-0410-b5e6-96231b3b80d8
* Prune utf8 chars in comments.NAKAMURA Takumi2013-10-281-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193512 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/R600: Un-tab-ify.NAKAMURA Takumi2013-10-283-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193510 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Replace ffs(x) - 1 with countTrailingZeros(x)Tom Stellard2013-10-231-1/+1
| | | | | | ffs(x) broke the mingw buildbot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193225 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: fix MIMG writemask adjustementTom Stellard2013-10-231-6/+21
| | | | | | | | | | | | | This fixes piglit: - shaders/glsl-fs-texture2d-masked - shaders/glsl-fs-texture2d-masked-4 Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193222 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix handling of vector kernel argumentsTom Stellard2013-10-239-35/+131
| | | | | | | | | | The SelectionDAGBuilder was promoting vector kernel arguments to legal types, but this won't work for R600 and SI since kernel arguments are stored in memory and can't be promoted. In order to handle vector arguments correctly we need to look at the original types from the LLVM IR function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193215 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add support for i64 bitwise orTom Stellard2013-10-231-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193213 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32Tom Stellard2013-10-233-2/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193212 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Don't assert on SCC usageMatt Arsenault2013-10-221-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193198 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Use llvm_unreachable() for an always false assertTom Stellard2013-10-221-2/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193183 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Fix warning on non-asserts buildTom Stellard2013-10-221-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193180 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Simplify handling of private address spaceTom Stellard2013-10-2213-436/+95
| | | | | | | | | | | | | | | | | | The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193179 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Remove unused InstrInfo::getMovImmInstr() functionTom Stellard2013-10-225-31/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193178 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Remove \ at EOL from ascii art comments.Benjamin Kramer2013-10-181-4/+4
| | | | | | | Completely harmless, but GCC likes to warn about it even when the next line is a comment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192974 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix a crash in the AMDILCFGStructurizerTom Stellard2013-10-161-2/+68
| | | | | | | | | | | We were calling llvm_unreachable() when failing to optimize the branch into if case. However, it is still possible for us to structurize the CFG by duplicating blocks even if this optimization fails. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192813 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Remove some dead code from the AMDILCFGStructurizerTom Stellard2013-10-161-21/+4
| | | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192812 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typoMatt Arsenault2013-10-151-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192752 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix missing C++ mode thing in headerMatt Arsenault2013-10-151-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192751 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Remove some leftover MI dump callVincent Lejeune2013-10-152-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192743 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: improve dump of S_WAITCNTVincent Lejeune2013-10-133-1/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192557 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Add SinkingPass before ISelVincent Lejeune2013-10-131-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192556 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Support byval argumentsVincent Lejeune2013-10-132-2/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192555 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use masked read sel for texture instructionsVincent Lejeune2013-10-131-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192554 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: fix swizzle exportVincent Lejeune2013-10-131-5/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192553 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Clear the VPM bit of export instructions.Vincent Lejeune2013-10-131-4/+4
| | | | | | | It makes apparently no change it to set this bit or not but the docs recommand to left it cleared. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192552 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Store disassembly in a special ELF section when feature +DumpCode is ↵Tom Stellard2013-10-123-14/+83
| | | | | | | | | | enabled. Patch by: Jay Cornwall Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192523 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typoMatt Arsenault2013-10-111-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192499 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typoMatt Arsenault2013-10-101-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192406 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Fix trunc i64 to i32 on SIMatt Arsenault2013-10-101-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192375 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP*Tom Stellard2013-10-105-4/+142
| | | | | | | The function is used by the machine verifier and checks that VOP* instructions have legal operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192367 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Define a separate MIMG instruction for each possible output value typeTom Stellard2013-10-105-35/+90
| | | | | | | | | | | | | During instruction selection, we rewrite the destination register class for MIMG instructions based on their writemasks. This creates machine verifier errors since the new register class does not match the register class in the MIMG instruction definition. We can avoid this by defining different MIMG instructions for each possible destination type and then switching to the correct instruction when we change the register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192365 91177308-0d34-0410-b5e6-96231b3b80d8
* R600/SI: Mark the EXEC register as reservedTom Stellard2013-10-101-0/+1
| | | | | | | | | This prevents the machine verifier from complaining about uses of an undefined physical register. Reviewed-by: Vincent Lejeune<vljn at ovi.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192364 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Use StructurizeCFGPass for non SI targetsTom Stellard2013-10-106-2/+18
| | | | | | | | | | | | | | | StructurizeCFG pass allows to make complex cfg reducible ; it allows a lot of shader from shadertoy (which exhibits complex control flow constructs) to works correctly with respect to CFG handling (and allow us to detect potential bug in other part of the backend). We provide a cmd line argument to disable the pass for debug purpose. Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192363 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a MCTargetStreamer interface.Rafael Espindola2013-10-081-1/+1
| | | | | | | | | | | | | This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: Add a ldptr intrinsic to support MSAA.Vincent Lejeune2013-10-023-1/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191838 91177308-0d34-0410-b5e6-96231b3b80d8
* R600: add a pass that merges clauses.Vincent Lejeune2013-10-017-2/+232
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191790 91177308-0d34-0410-b5e6-96231b3b80d8
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