aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/Sparc/SparcInstrFormats.td
Commit message (Collapse)AuthorAgeFilesLines
* Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,Venkatraman Govindaraju2013-06-041-4/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183243 91177308-0d34-0410-b5e6-96231b3b80d8
* Use i32 for all SPARC shift amounts, even in 64-bit mode.Jakob Stoklund Olesen2013-04-141-4/+4
| | | | | | Test case by llvm-stress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179477 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 64-bit shift instructions.Jakob Stoklund Olesen2013-04-021-0/+37
| | | | | | | | | | | SPARC v9 defines new 64-bit shift instructions. The 32-bit shift right instructions are still usable as zero and sign extensions. This adds new F3_Sr and F3_Si instruction formats that probably should be used for the 32-bit shifts as well. They don't really encode an simm13 field. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178525 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-3/+3
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-16/+17
| | | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a couple of multiclass patterns to factor some integer ops.Chris Lattner2006-09-011-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30039 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename SPARC V8 target to be the LLVM SPARC target.Chris Lattner2006-02-051-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25985 91177308-0d34-0410-b5e6-96231b3b80d8
* Push ops list, asm string, and pattern all the way up to InstV8. Move theChris Lattner2005-12-181-27/+24
| | | | | | | InstV8 class to the InstrFormats file where it belongs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24824 91177308-0d34-0410-b5e6-96231b3b80d8
* Add initial conditional branch support. This doesn't actually work yet dueChris Lattner2005-12-181-1/+3
| | | | | | | to a bug in the scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24807 91177308-0d34-0410-b5e6-96231b3b80d8
* Give patterns to F3_3 instructionsChris Lattner2005-12-171-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24800 91177308-0d34-0410-b5e6-96231b3b80d8
* Use sethi to build large immediates with zeros at the bottomChris Lattner2005-12-171-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24779 91177308-0d34-0410-b5e6-96231b3b80d8
* Add empty patterns to all F3_1 instructionsChris Lattner2005-12-171-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24776 91177308-0d34-0410-b5e6-96231b3b80d8
* Add empty patterns for F3_2 instructionsChris Lattner2005-12-171-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24771 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert the remaining instructions over, branches and calls. Fix a coupleChris Lattner2005-12-171-2/+4
| | | | | | | minor bugs git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24762 91177308-0d34-0410-b5e6-96231b3b80d8
* convert FP instructions to use an asmstring and operand list, allowing FPChris Lattner2005-12-171-2/+5
| | | | | | | programs to work on V8 again git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24761 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a couple more instrsChris Lattner2005-12-161-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24744 91177308-0d34-0410-b5e6-96231b3b80d8
* Autogenerate asmprinter for F3_2 instructionsChris Lattner2005-12-161-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24741 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch F3_1 instructions over to use AsmStringsChris Lattner2005-12-161-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24740 91177308-0d34-0410-b5e6-96231b3b80d8
* Add operand info for F3_[12] instructions, getting V8 back to basic ↵Chris Lattner2005-12-161-2/+6
| | | | | | | | | | functionality. With this, Regression/CodeGen/SparcV8/basictest.ll now passes. Lets hear it for regression tests :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24738 91177308-0d34-0410-b5e6-96231b3b80d8
* Class F2_1 already inherits the imm22 field from class F2Misha Brukman2004-10-141-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17001 91177308-0d34-0410-b5e6-96231b3b80d8
* * In the F3_1 class, default asi to 0 because it's not currently usedMisha Brukman2004-10-141-2/+1
| | | | | | | * In the F3_3 class, remove mention of asi because it's not part of the format git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16999 91177308-0d34-0410-b5e6-96231b3b80d8
* Combine the F2 and F3 instruction classes into one file for simplicityMisha Brukman2004-09-221-0/+97
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16484 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-11-17 16:26:43 +0000