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path: root/lib/Target/Sparc/SparcRegisterInfo.td
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* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-3/+3
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a CoveredBySubRegs property to Register descriptions.Jakob Stoklund Olesen2012-01-181-0/+1
| | | | | | | | | | | | | | | | When set, this bit indicates that a register is completely defined by the value of its sub-registers. Use the CoveredBySubRegs property to infer which super-registers are call-preserved given a list of callee-saved registers. For example, the ARM registers D8-D15 are callee-saved. This now automatically implies that Q4-Q7 are call-preserved. Conversely, Win64 callees save XMM6-XMM15, but the corresponding YMM6-YMM15 registers are not call-preserved because they are not fully defined by their sub-registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148363 91177308-0d34-0410-b5e6-96231b3b80d8
* Use set operations instead of plain lists to enumerate register classes.Jakob Stoklund Olesen2011-06-151-18/+16
| | | | | | | | | | | | This simplifies many of the target description files since it is common for register classes to be related or contain sequences of numbered registers. I have verified that this doesn't change the files generated by TableGen for ARM and X86. It alters the allocation order of MBlaze GPR and Mips FGR32 registers, but I believe the change is benign. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133105 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove custom allocation order boilerplate that is no longer needed.Jakob Stoklund Olesen2011-06-091-15/+1
| | | | | | | | | | | | | | | | | | | | The register allocators automatically filter out reserved registers and place the callee saved registers last in the allocation order, so custom methods are no longer necessary just for that. Some targets still use custom allocation orders: ARM/Thumb: The high registers are removed from GPR in thumb mode. The NEON allocation orders prefer to use non-VFP2 registers first. X86: The GR8 classes omit AH-DH in x86-64 mode to avoid REX trouble. SystemZ: Some of the allocation orders are omitting R12 aliases without explanation. I don't understand this target well enough to fix that. It looks like all the boilerplate could be removed by reserving the right registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132781 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix to match the dwarf register numbers that gdb uses.Rafael Espindola2011-05-291-16/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132278 91177308-0d34-0410-b5e6-96231b3b80d8
* Multiple SPARC backend fixes: added Y register; updated select_cc, subx, ↵Venkatraman Govindaraju2010-12-281-0/+3
| | | | | | | | | subxcc defs/uses; and fixed CustomInserter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122607 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-0/+6
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104704 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Replace the SubRegSet tablegen class with a less error-prone mechanism."Jakob Stoklund Olesen2010-05-261-6/+0
| | | | | | This reverts commit 104654. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104660 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace the SubRegSet tablegen class with a less error-prone mechanism.Jakob Stoklund Olesen2010-05-261-0/+6
| | | | | | | | | | | | | | | | A Register with subregisters must also provide SubRegIndices for adressing the subregisters. TableGen automatically inherits indices for sub-subregisters to minimize typing. CompositeIndices may be specified for the weirder cases such as the XMM sub_sd index that returns the same register, and ARM NEON Q registers where both D subregs have ssub_0 and ssub_1 sub-subregs. It is now required that all subregisters are named by an index, and a future patch will also require inherited subregisters to be named. This is necessary to allow composite subregister indices to be reduced to a single index. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104654 91177308-0d34-0410-b5e6-96231b3b80d8
* several major improvements to the sparc backend: support for weak linkageChris Lattner2009-09-151-2/+10
| | | | | | | | and PIC codegen. Patch by Venkatraman Govindaraju! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81877 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* Use TableGen to emit information for dwarf register numbers. Anton Korobeynikov2007-11-111-80/+80
| | | | | | | | | This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc.Evan Cheng2007-07-131-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39843 91177308-0d34-0410-b5e6-96231b3b80d8
* Constify some methods. Patch provided by Anton Vayvod, thanks!Chris Lattner2006-08-171-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29756 91177308-0d34-0410-b5e6-96231b3b80d8
* D'oh - should be even numbered.Jim Laskey2006-03-241-15/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27088 91177308-0d34-0410-b5e6-96231b3b80d8
* Add dwarf register numbering to register data.Jim Laskey2006-03-241-31/+80
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27081 91177308-0d34-0410-b5e6-96231b3b80d8
* Update to new-style flags usage, simplifying the .td fileChris Lattner2006-02-101-9/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26106 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename SPARC V8 target to be the LLVM SPARC target.Chris Lattner2006-02-051-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25985 91177308-0d34-0410-b5e6-96231b3b80d8
* Reserve G1 for frame offset stuff and use it to handle large stack frames.Chris Lattner2005-12-201-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For example, instead of emitting this: test: save -40112, %o6, %o6 ;; imm too large add %i6, -40016, %o0 ;; imm too large call caller nop restore %g0, %g0, %g0 retl nop emit this: test: sethi 4194264, %g1 or %g1, 848, %g1 save %o6, %g1, %o6 sethi 4194264, %g1 add %g1, %i6, %g1 add %i1, 944, %o0 call caller nop restore %g0, %g0, %g0 retl nop which doesn't cause the assembler to barf. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24880 91177308-0d34-0410-b5e6-96231b3b80d8
* Elimiante SP and FP, which weren't members of the IntRegs register classChris Lattner2005-12-191-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24844 91177308-0d34-0410-b5e6-96231b3b80d8
* Add initial conditional branch support. This doesn't actually work yet dueChris Lattner2005-12-181-0/+8
| | | | | | | to a bug in the scheduler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24807 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for multiply, simplify Y register handling stuff, add RDY ↵Chris Lattner2005-12-171-7/+0
| | | | | | instruction git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24796 91177308-0d34-0410-b5e6-96231b3b80d8
* Support multiple ValueTypes per RegisterClass, needed for upcoming vectorNate Begeman2005-12-011-3/+3
| | | | | | | work. This change has no effect on generated code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24563 91177308-0d34-0410-b5e6-96231b3b80d8
* Split RegisterClass 'Methods' into MethodProtos and MethodBodiesChris Lattner2005-08-191-2/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22929 91177308-0d34-0410-b5e6-96231b3b80d8
* put reg classes in namespacesChris Lattner2005-08-191-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22922 91177308-0d34-0410-b5e6-96231b3b80d8
* Make this file self-contained.Brian Gaeke2004-12-101-1/+62
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@18736 91177308-0d34-0410-b5e6-96231b3b80d8
* Allocate fewer registers and tighten up alignment restrictions.Brian Gaeke2004-11-181-4/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17929 91177308-0d34-0410-b5e6-96231b3b80d8
* SparcV8 int regs are not only 32-bits in width, but they are 32-bit aligned!Misha Brukman2004-09-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16526 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the copy-pasto that Brian noticed: V8 int regs are 32-bits wide, not 64.Misha Brukman2004-09-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16518 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the V8/V9 shared register file descriptionMisha Brukman2004-09-221-77/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16485 91177308-0d34-0410-b5e6-96231b3b80d8
* Changes to make this work with Jason's patch. I checked this by hand, butChris Lattner2004-09-131-48/+50
| | | | | | | | would appreciate if others would also look at this to make sure I didn't botch something obvious git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@16312 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert bytes to bits in alignmentChris Lattner2004-08-211-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15971 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the double-fp pseudo registers be "NamedRegs".Brian Gaeke2004-06-241-5/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14366 91177308-0d34-0410-b5e6-96231b3b80d8
* The long integer pseudo-regs are history. So long, we hardly knew ye.Brian Gaeke2004-06-241-30/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14364 91177308-0d34-0410-b5e6-96231b3b80d8
* Add pseudo-registers and register class for 64-bit integer values.Brian Gaeke2004-06-221-0/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14332 91177308-0d34-0410-b5e6-96231b3b80d8
* Mess around with allocation order. In particular, I think we ought to beBrian Gaeke2004-06-181-3/+3
| | | | | | | using the local & in regs first because they are not clobbered by calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14228 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge my changes with briansChris Lattner2004-04-071-6/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12736 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the "Y" register, used by MUL & DIV.Brian Gaeke2004-04-071-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12734 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid allocating special registers a bit more robustlyChris Lattner2004-03-081-3/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12207 91177308-0d34-0410-b5e6-96231b3b80d8
* Hack it so we do not try to allocate values to G0.Brian Gaeke2004-03-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12184 91177308-0d34-0410-b5e6-96231b3b80d8
* Double-FP pseudo-registers.Brian Gaeke2004-03-041-3/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12112 91177308-0d34-0410-b5e6-96231b3b80d8
* Floating point regsBrian Gaeke2004-03-041-2/+17
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12110 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement initial prolog/epilog code insertion methods.Chris Lattner2004-02-291-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11979 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an instruction selector capable of selecting 'ret void'Chris Lattner2004-02-291-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11973 91177308-0d34-0410-b5e6-96231b3b80d8
* Tab completion is our friend.Chris Lattner2004-02-281-0/+42
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11957 91177308-0d34-0410-b5e6-96231b3b80d8
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