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* Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb2008-03-161-0/+8
| | | | | | LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove isImplicitDef TargetInstrDesc flag.Evan Cheng2008-03-151-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48381 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace all target specific implicit def instructions with a target ↵Evan Cheng2008-03-151-0/+7
| | | | | | independent one: TargetInstrInfo::IMPLICIT_DEF. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommitting parts of r48130. These do not appear to cause the observed ↵Christopher Lamb2008-03-111-4/+8
| | | | | | failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng2008-03-101-8/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow insert_subreg into implicit, target-specific values. Christopher Lamb2008-03-101-4/+8
| | | | | | | | Change insert/extract subreg instructions to be able to be used in TableGen patterns. Use the above features to reimplement an x86-64 pseudo instruction as a pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename PrintableName to Name.Bill Wendling2008-02-261-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47629 91177308-0d34-0410-b5e6-96231b3b80d8
* Change "Name" to "AsmName" in the target register info. Gee, a refactoring toolBill Wendling2008-02-261-1/+1
| | | | | | | would have been a Godsend here! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47625 91177308-0d34-0410-b5e6-96231b3b80d8
* Some platforms use the same name for 32-bit and 64-bit registers (likeBill Wendling2008-02-241-0/+1
| | | | | | | | | | %r3 on PPC) in their ASM files. However, it's hard for humans to read during debugging. Adding a new field to the register data that lets you specify a different name to be printed than the one that goes into the ASM file -- %x3 instead of %r3, for instance. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47534 91177308-0d34-0410-b5e6-96231b3b80d8
* Move some useful operands up into the all-targets .tdNate Begeman2008-02-141-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47115 91177308-0d34-0410-b5e6-96231b3b80d8
* SDIsel processes llvm.dbg.declare by recording the variable debug ↵Evan Cheng2008-02-021-1/+8
| | | | | | | | | | information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc. Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes. For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an extra operand to LABEL nodes which distinguishes between debug, EH, ↵Evan Cheng2008-01-311-1/+1
| | | | | | or misc labels. This fixes the EH breakage. However I am not convinced this is *the* solution. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46609 91177308-0d34-0410-b5e6-96231b3b80d8
* Start inferring side effect information more aggressively, and fix many bugs ↵Chris Lattner2008-01-101-6/+9
| | | | | | | | | | | | | | | in the x86 backend where instructions were not marked maystore/mayload, and perf issues where instructions were not marked neverHasSideEffects. It would be really nice if we could write patterns for copy instructions. I have audited all the x86 instructions down to MOVDQAmr. The flags on others and on other targets are probably not right in all cases, but no clients currently use this info that are enabled by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45829 91177308-0d34-0410-b5e6-96231b3b80d8
* add a new bit.Chris Lattner2008-01-071-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45726 91177308-0d34-0410-b5e6-96231b3b80d8
* remove a dead field.Chris Lattner2008-01-071-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45685 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.Chris Lattner2008-01-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* As per feedback, revised comments to (hopefully) make the different side effectBill Wendling2007-12-171-3/+12
| | | | | | | flags clearer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45120 91177308-0d34-0410-b5e6-96231b3b80d8
* Add flags to indicate that there are "never" side effects or that there "may be"Bill Wendling2007-12-141-0/+5
| | | | | | | side effects for machine instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45022 91177308-0d34-0410-b5e6-96231b3b80d8
* Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always ↵Evan Cheng2007-12-121-0/+1
| | | | | | re-materializable and they should not be spilled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44960 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a flag for indirect branch instructions.Owen Anderson2007-11-121-0/+1
| | | | | | | Target maintainers: please check that the instructions for your target are correctly marked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44012 91177308-0d34-0410-b5e6-96231b3b80d8
* Clarify the meaning of '-2' register numberAnton Korobeynikov2007-11-111-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43998 91177308-0d34-0410-b5e6-96231b3b80d8
* Use TableGen to emit information for dwarf register numbers. Anton Korobeynikov2007-11-111-5/+5
| | | | | | | | | This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8
* Add CopyCost to TargetRegisterClass. This specifies the cost of copying a valueEvan Cheng2007-09-191-0/+6
| | | | | | | between two registers in the specific class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42123 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.Evan Cheng2007-09-111-7/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
* Add target independent MachineInstr's to represent subreg insert/extract in ↵Christopher Lamb2007-07-261-0/+12
| | | | | | MBB's. PR1350 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40518 91177308-0d34-0410-b5e6-96231b3b80d8
* No more noResults.Evan Cheng2007-07-211-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
* Change instruction description to split OperandList into OutOperandList andEvan Cheng2007-07-191-6/+14
| | | | | | | | | | | | | | | | InOperandList. This gives one piece of important information: # of results produced by an instruction. An example of the change: def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; => def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), "add{l} {$src2, $dst|$dst, $src2}", [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>; git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove clobbersPred.Evan Cheng2007-07-101-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@38500 91177308-0d34-0410-b5e6-96231b3b80d8
* Do away with ImmutablePredicateOperand.Evan Cheng2007-07-061-8/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37959 91177308-0d34-0410-b5e6-96231b3b80d8
* Add OptionalDefOperand to stand for optionally defined result.Evan Cheng2007-07-061-7/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37930 91177308-0d34-0410-b5e6-96231b3b80d8
* - Added zero_reg def to stand for register 0.Evan Cheng2007-07-051-2/+19
| | | | | | | - Added two variants of PredicateOperand: ImmutablePredicateOperand, whose predicate does not change after isel; PredicateDefOperand, which represent a predicate defintion operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37892 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert the earlier change that removed the M_REMATERIALIZABLE machineDan Gohman2007-06-261-0/+1
| | | | | | | | | | instruction flag, and use the flag along with a virtual member function hook for targets to override if there are instructions that are only trivially rematerializable with specific operands (i.e. constant pool loads). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37728 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoadDan Gohman2007-06-191-1/+0
| | | | | | | | | | | with a general target hook to identify rematerializable instructions. Some instructions are only rematerializable with specific operands, such as loads from constant pools, while others are always rematerializable. This hook allows both to be identified as being rematerializable with the same mechanism. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37644 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit.Evan Cheng2007-06-191-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37643 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support to tablegen for specifying subregister classes on a per register ↵Christopher Lamb2007-06-131-0/+4
| | | | | | class basis. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37572 91177308-0d34-0410-b5e6-96231b3b80d8
* Added clobbersPred.Evan Cheng2007-06-061-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37466 91177308-0d34-0410-b5e6-96231b3b80d8
* Added isPredicable bit to class Instruction.Evan Cheng2007-05-161-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37117 91177308-0d34-0410-b5e6-96231b3b80d8
* PredicateOperand can be used as a normal operand for isel.Evan Cheng2007-05-081-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36947 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an "implies" field to features. This indicates that, if the currentBill Wendling2007-05-041-1/+7
| | | | | | | | | feature is set, then the features in the implied list should be set also. The opposite is also enforced: if a feature in the implied list isn't set, then the feature that owns that implies list shouldn't be set either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36756 91177308-0d34-0410-b5e6-96231b3b80d8
* expose HonorSignDependentRoundingFPMathOption to .td filesChris Lattner2007-05-031-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36658 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm bug #1350, parts 1, 2, and 3.Nate Begeman2007-05-011-7/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36618 91177308-0d34-0410-b5e6-96231b3b80d8
* Add sub-registers sets.Evan Cheng2007-04-201-1/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36278 91177308-0d34-0410-b5e6-96231b3b80d8
* Added isReMaterializable.Evan Cheng2007-03-191-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35160 91177308-0d34-0410-b5e6-96231b3b80d8
* Add calling convention infoChris Lattner2007-02-271-1/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34661 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typos in comments.Dan Gohman2007-02-201-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34456 91177308-0d34-0410-b5e6-96231b3b80d8
* Make LABEL a builtin opcode.Jim Laskey2007-01-261-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
* Comment.Evan Cheng2007-01-121-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33114 91177308-0d34-0410-b5e6-96231b3b80d8
* add a new field needed by the code emitter generator.Chris Lattner2006-11-151-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31768 91177308-0d34-0410-b5e6-96231b3b80d8
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