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* Remove the OrigVT member from AtomicSDNode, as it is redundant withDan Gohman2008-06-251-12/+12
| | | | | | | the base SDNode's VTList. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52722 91177308-0d34-0410-b5e6-96231b3b80d8
* Added MemOperands to Atomic operations since Atomics touches memory.Mon P Wang2008-06-251-35/+36
| | | | | | | | | Added abstract class MemSDNode for any Node that have an associated MemOperand Changed atomic.lcs => atomic.cmp.swap, atomic.las => atomic.load.add, and atomic.lss => atomic.load.sub git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52706 91177308-0d34-0410-b5e6-96231b3b80d8
* add missing atomic intrinsic from gccAndrew Lenharth2008-06-141-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52270 91177308-0d34-0410-b5e6-96231b3b80d8
* Wrap MVT::ValueType in a struct to get type safetyDuncan Sands2008-06-061-4/+4
| | | | | | | | | | | | | | | | | and better control the abstraction. Rename the type to MVT. To update out-of-tree patches, the main thing to do is to rename MVT::ValueType to MVT, and rewrite expressions like MVT::getSizeInBits(VT) in the form VT.getSizeInBits(). Use VT.getSimpleVT() to extract a MVT::SimpleValueType for use in switch statements (you will get an assert failure if VT is an extended value type - these shouldn't exist after type legalization). This results in a small speedup of codegen and no new testsuite failures (x86-64 linux). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the DAGISelEmitter to not compute the variable_ops operandDan Gohman2008-05-311-2/+1
| | | | | | | | | | | | index for the input pattern in terms of the output pattern. Instead keep track of how many fixed operands the input pattern actually has, and have the input matching code pass the output-emitting function that index value. This simplifies the code, disentangles variables_ops from the support for predication operations, and makes variable_ops more robust. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51808 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a tblgen problem handling variable_ops in tblgen instructionDan Gohman2008-05-291-0/+1
| | | | | | | | | | | | | definitions. This adds a new construct, "discard", for indicating that a named node in the input matching pattern is to be discarded, instead of corresponding to a node in the output pattern. This allows tblgen to know where the arguments for the varaible_ops are supposed to begin. This fixes "rdar://5791600", whatever that is ;-). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51699 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for vicmp/vfcmp codegen, more legalize support coming.Nate Begeman2008-05-121-0/+1
| | | | | | | This is necessary to unbreak the build. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50988 91177308-0d34-0410-b5e6-96231b3b80d8
* Added addition atomic instrinsics and, or, xor, min, and max.Mon P Wang2008-05-051-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
* Make insert_subreg a two-address instruction, vastly simplifying ↵Christopher Lamb2008-03-161-8/+0
| | | | | | LowerSubregs pass. Add a new TII, subreg_to_reg, which is like insert_subreg except that it takes an immediate implicit value to insert into rather than a register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48412 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of a pseudo instruction and replace it with subreg based operation ↵Christopher Lamb2008-03-131-1/+6
| | | | | | | | | | on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement x86 support for @llvm.prefetch. It corresponds to prefetcht{0|1|2} ↵Evan Cheng2008-03-081-7/+16
| | | | | | and prefetchnta instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48042 91177308-0d34-0410-b5e6-96231b3b80d8
* Atomic op support. If any gcc test uses __sync builtins, it might start ↵Andrew Lenharth2008-02-211-0/+91
| | | | | | failing on archs that haven't implemented them yet git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47430 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm.memory.barrier, and impl for x86 and alphaAndrew Lenharth2008-02-161-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47204 91177308-0d34-0410-b5e6-96231b3b80d8
* Change how FP immediates are handled. Nate Begeman2008-02-141-2/+1
| | | | | | | | | | | | | | | 1) ConstantFP is now expand by default 2) ConstantFP is not turned into TargetConstantFP during Legalize if it is legal. This allows ConstantFP to be handled like Constant, allowing for targets that can encode FP immediates as MachineOperands. As a bonus, fix up Itanium FP constants, which now correctly match, and match more constants! Hooray. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47121 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable SSE4 codegen and pattern matching.Nate Begeman2008-02-111-2/+2
| | | | | | | Add some notes to the README. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46949 91177308-0d34-0410-b5e6-96231b3b80d8
* Tablegen support for insert & extract element matchingNate Begeman2008-02-091-0/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46901 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow ComplexExpressions in InstrInfo.td files to be slightly more... ↵Christopher Lamb2008-01-311-1/+9
| | | | | | | | | | | complex! ComplexExpressions can now have attributes which affect how TableGen interprets the pattern when generating matchin code. The first (and currently, only) attribute causes the immediate parent node of the ComplexPattern operand to be passed into the matching code rather than the node at the root of the entire DAG containing the pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46606 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor the addressing mode and the load/store VT out of LoadSDNodeDan Gohman2008-01-301-29/+29
| | | | | | | | | and StoreSDNode into their common base class LSBaseSDNode. Member functions getLoadedVT and getStoredVT are replaced with the common getMemoryVT to simplify code that will handle both loads and stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46538 91177308-0d34-0410-b5e6-96231b3b80d8
* This commit changes:Chris Lattner2008-01-171-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Legalize now always promotes truncstore of i1 to i8. 2. Remove patterns and gunk related to truncstore i1 from targets. 3. Rename the StoreXAction stuff to TruncStoreAction in TLI. 4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions. 5. Mark a wide variety of invalid truncstores as such in various targets, e.g. X86 currently doesn't support truncstore of any of its integer types. 6. Add legalize support for truncstores with invalid value input types. 7. Add a dag combine transform to turn store(truncate) into truncstore when safe. The later allows us to compile CodeGen/X86/storetrunc-fp.ll to: _foo: fldt 20(%esp) fldt 4(%esp) faddp %st(1) movl 36(%esp), %eax fstps (%eax) ret instead of: _foo: subl $4, %esp fldt 24(%esp) fldt 8(%esp) faddp %st(1) fstps (%esp) movl 40(%esp), %eax movss (%esp), %xmm0 movss %xmm0, (%eax) addl $4, %esp ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
* rename SDTRet -> SDTNone.Chris Lattner2008-01-151-2/+4
| | | | | | | Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8
* add SDNPSideEffect node property declarationChris Lattner2008-01-101-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45825 91177308-0d34-0410-b5e6-96231b3b80d8
* add SDNPMayLoad to the 'load' sdnode definition. This is enough to get all ↵Chris Lattner2008-01-101-1/+3
| | | | | | | | | the x86 instructions (with patterns) that load memory marked, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45818 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-061-2/+5
| | | | | | | | | | | | instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45654 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
* add a immAllZerosV_bc pattern fragment for consistency with others.Chris Lattner2007-11-241-3/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44303 91177308-0d34-0410-b5e6-96231b3b80d8
* Unifacalize the CALLSEQ{START,END} stuff.Bill Wendling2007-11-131-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44045 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename keyword "modify" -> "implicit".Evan Cheng2007-09-251-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42282 91177308-0d34-0410-b5e6-96231b3b80d8
* Initial support for multi-result patterns:Evan Cheng2007-09-121-0/+2
| | | | | | | | | | | | | 1. [(set GR32:$dst, (add GR32:$src1, GR32:$src2)), (modify EFLAGS)] This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS. 2. def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()> Similar to #1 except this is used for def : Pat patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41897 91177308-0d34-0410-b5e6-96231b3b80d8
* Long double patch 4 of N: initial x87 implementation.Dale Johannesen2007-08-051-0/+14
| | | | | | | Lots of problems yet but some simple things work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40847 91177308-0d34-0410-b5e6-96231b3b80d8
* Add selection DAG nodes for subreg insert/extract. PR1350Christopher Lamb2007-07-261-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40516 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comments about vectors to use the current wording.Dan Gohman2007-07-161-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39921 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement "general dynamic", "initial exec" and "local exec" TLS models forLauro Ramos Venancio2007-04-201-0/+4
| | | | | | | X86 32 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36283 91177308-0d34-0410-b5e6-96231b3b80d8
* Make LABEL a builtin opcode.Jim Laskey2007-01-261-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33537 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix predicates for unindexed stores so they don't accidentally match indexedChris Lattner2006-11-141-33/+39
| | | | | | | stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31735 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename ISD::MemOpAddrMode to ISD::MemIndexedModeEvan Cheng2006-11-091-12/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31596 91177308-0d34-0410-b5e6-96231b3b80d8
* Added indexed store node and patfrag's.Evan Cheng2006-11-081-11/+131
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31576 91177308-0d34-0410-b5e6-96231b3b80d8
* Change load PatFrag to ignore indexed load.Evan Cheng2006-10-261-31/+62
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31210 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng2006-10-131-12/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
* Add properties to ComplexPattern.Evan Cheng2006-10-111-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30891 91177308-0d34-0410-b5e6-96231b3b80d8
* Naming consistency.Evan Cheng2006-10-111-13/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30878 91177308-0d34-0410-b5e6-96231b3b80d8
* Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng2006-10-091-16/+74
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
* Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add anEvan Cheng2006-10-041-12/+10
| | | | | | | extra operand to LOADX to specify the exact value extension type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30714 91177308-0d34-0410-b5e6-96231b3b80d8
* Vector extract / insert index operand should have ptr type.Evan Cheng2006-06-151-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28798 91177308-0d34-0410-b5e6-96231b3b80d8
* JumpTable support! What this represents is working asm and jit support forNate Begeman2006-04-221-0/+9
| | | | | | | | | x86 and ppc for 100% dense switch statements when relocations are non-PIC. This support will be extended and enhanced in the coming days to support PIC, and less dense forms of jump tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
* Renamed AddedCost to AddedComplexity.Evan Cheng2006-04-191-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27843 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow "let AddedCost = n in" to increase pattern complexity.Evan Cheng2006-04-191-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27834 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new vnot_conv predicate for matching vnot's where the allones vector isChris Lattner2006-04-151-0/+6
| | | | | | | bitconverted from some other type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27724 91177308-0d34-0410-b5e6-96231b3b80d8
* Add vector_extract and vector_insert nodes.Evan Cheng2006-03-311-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27303 91177308-0d34-0410-b5e6-96231b3b80d8
* Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum ↵Chris Lattner2006-03-281-3/+3
| | | | | | value. Split them into separate enums. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27201 91177308-0d34-0410-b5e6-96231b3b80d8
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