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* This commit changes:Chris Lattner2008-01-171-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Legalize now always promotes truncstore of i1 to i8. 2. Remove patterns and gunk related to truncstore i1 from targets. 3. Rename the StoreXAction stuff to TruncStoreAction in TLI. 4. Make the TLI TruncStoreAction table a 2d table to handle from/to conversions. 5. Mark a wide variety of invalid truncstores as such in various targets, e.g. X86 currently doesn't support truncstore of any of its integer types. 6. Add legalize support for truncstores with invalid value input types. 7. Add a dag combine transform to turn store(truncate) into truncstore when safe. The later allows us to compile CodeGen/X86/storetrunc-fp.ll to: _foo: fldt 20(%esp) fldt 4(%esp) faddp %st(1) movl 36(%esp), %eax fstps (%eax) ret instead of: _foo: subl $4, %esp fldt 24(%esp) fldt 8(%esp) faddp %st(1) fstps (%esp) movl 40(%esp), %eax movss (%esp), %xmm0 movss %xmm0, (%eax) addl $4, %esp ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46140 91177308-0d34-0410-b5e6-96231b3b80d8
* rename SDTRet -> SDTNone.Chris Lattner2008-01-151-2/+4
| | | | | | | Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46017 91177308-0d34-0410-b5e6-96231b3b80d8
* add SDNPSideEffect node property declarationChris Lattner2008-01-101-0/+1
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* add SDNPMayLoad to the 'load' sdnode definition. This is enough to get all ↵Chris Lattner2008-01-101-1/+3
| | | | | | | | | the x86 instructions (with patterns) that load memory marked, for example. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45818 91177308-0d34-0410-b5e6-96231b3b80d8
* rename isStore -> mayStore to more accurately reflect what it captures.Chris Lattner2008-01-061-1/+1
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* Change the 'isStore' inferrer to look for 'SDNPMayStore' Chris Lattner2008-01-061-2/+5
| | | | | | | | | | | | instead of "ISD::STORE". This allows us to mark target-specific dag nodes as storing (such as ppc byteswap stores). This allows us to remove more explicit isStore flags from the .td files. Finally, add a warning for when a .td file contains an explicit isStore and tblgen is able to infer it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45654 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove attribution from file headers, per discussion on llvmdev.Chris Lattner2007-12-291-2/+2
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* add a immAllZerosV_bc pattern fragment for consistency with others.Chris Lattner2007-11-241-3/+6
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* Unifacalize the CALLSEQ{START,END} stuff.Bill Wendling2007-11-131-0/+5
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* Rename keyword "modify" -> "implicit".Evan Cheng2007-09-251-1/+1
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* Initial support for multi-result patterns:Evan Cheng2007-09-121-0/+2
| | | | | | | | | | | | | 1. [(set GR32:$dst, (add GR32:$src1, GR32:$src2)), (modify EFLAGS)] This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS. 2. def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()> Similar to #1 except this is used for def : Pat patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41897 91177308-0d34-0410-b5e6-96231b3b80d8
* Long double patch 4 of N: initial x87 implementation.Dale Johannesen2007-08-051-0/+14
| | | | | | | Lots of problems yet but some simple things work. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40847 91177308-0d34-0410-b5e6-96231b3b80d8
* Add selection DAG nodes for subreg insert/extract. PR1350Christopher Lamb2007-07-261-0/+5
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* Fix comments about vectors to use the current wording.Dan Gohman2007-07-161-1/+1
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* Implement "general dynamic", "initial exec" and "local exec" TLS models forLauro Ramos Venancio2007-04-201-0/+4
| | | | | | | X86 32 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36283 91177308-0d34-0410-b5e6-96231b3b80d8
* Make LABEL a builtin opcode.Jim Laskey2007-01-261-3/+0
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* Fix predicates for unindexed stores so they don't accidentally match indexedChris Lattner2006-11-141-33/+39
| | | | | | | stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31735 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename ISD::MemOpAddrMode to ISD::MemIndexedModeEvan Cheng2006-11-091-12/+12
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* Added indexed store node and patfrag's.Evan Cheng2006-11-081-11/+131
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31576 91177308-0d34-0410-b5e6-96231b3b80d8
* Change load PatFrag to ignore indexed load.Evan Cheng2006-10-261-31/+62
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31210 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.Evan Cheng2006-10-131-12/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
* Add properties to ComplexPattern.Evan Cheng2006-10-111-1/+3
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* Naming consistency.Evan Cheng2006-10-111-13/+13
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* Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.Evan Cheng2006-10-091-16/+74
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* Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add anEvan Cheng2006-10-041-12/+10
| | | | | | | extra operand to LOADX to specify the exact value extension type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30714 91177308-0d34-0410-b5e6-96231b3b80d8
* Vector extract / insert index operand should have ptr type.Evan Cheng2006-06-151-2/+2
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* JumpTable support! What this represents is working asm and jit support forNate Begeman2006-04-221-0/+9
| | | | | | | | | x86 and ppc for 100% dense switch statements when relocations are non-PIC. This support will be extended and enhanced in the coming days to support PIC, and less dense forms of jump tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
* Renamed AddedCost to AddedComplexity.Evan Cheng2006-04-191-4/+4
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* Allow "let AddedCost = n in" to increase pattern complexity.Evan Cheng2006-04-191-1/+2
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* Add a new vnot_conv predicate for matching vnot's where the allones vector isChris Lattner2006-04-151-0/+6
| | | | | | | bitconverted from some other type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27724 91177308-0d34-0410-b5e6-96231b3b80d8
* Add vector_extract and vector_insert nodes.Evan Cheng2006-03-311-0/+4
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* Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum ↵Chris Lattner2006-03-281-3/+3
| | | | | | value. Split them into separate enums. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27201 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed isBuildVectorAllOnesInteger to isBuildVectorAllOnes.Evan Cheng2006-03-271-1/+1
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* Add immAllZerosV helperEvan Cheng2006-03-261-0/+3
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* add a vnot helper node for matching 'not' on vectorsChris Lattner2006-03-251-2/+6
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* Add new intrinsic node definitions for tblgen useChris Lattner2006-03-251-0/+12
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* Shuffle some includes aroundChris Lattner2006-03-241-3/+0
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* expose intrinsic info to the targets.Chris Lattner2006-03-241-0/+3
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* x86 ISD::SCALAR_TO_VECTOR support.Evan Cheng2006-03-211-0/+2
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* Add a build_vector nodeChris Lattner2006-03-201-1/+1
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* add vector_shuffleChris Lattner2006-03-201-0/+16
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* add support for the bitconvert nodeChris Lattner2006-03-161-0/+3
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* relax fcopysignAndrew Lenharth2006-03-091-1/+4
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* fcopysign supportAndrew Lenharth2006-03-091-0/+1
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* remove the read/write port/io intrinsics.Chris Lattner2006-03-031-11/+0
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* kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBCNate Begeman2006-02-171-1/+8
| | | | | | | | and SUBE nodes that actually expose what's going on and allow for significant simplifications in the targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
* Whoops, didn't mean to check this in yet.Nate Begeman2006-02-171-8/+0
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* Add a missing and useful pat fragNate Begeman2006-02-171-2/+9
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* Targets all now request ConstantFP to be legalized into TargetConstantFP.Chris Lattner2006-01-291-1/+2
| | | | | | | 'fpimm' in .td files is now TargetConstantFP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25771 91177308-0d34-0410-b5e6-96231b3b80d8
* bswap implementationNate Begeman2006-01-141-0/+1
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