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* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-271-1/+2
| | | | | | | into XXXGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 table-generator and disassembler support for the AVXSean Callanan2011-03-151-0/+5
| | | | | | | | | | instruction set. This code adds support for the VEX prefix and for the YMM registers accessible on AVX-enabled architectures. Instruction table support that enables AVX instructions for the disassembler is in an upcoming patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127644 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug in the X86 disassembler where a member of theSean Callanan2011-02-211-4/+4
| | | | | | | | | X86 instruction decode structure was being interpreted as being in units of bits, although it is actually stored in units of bytes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126147 91177308-0d34-0410-b5e6-96231b3b80d8
* Make the disassembler tables const so they end up in read-only memory.Benjamin Kramer2010-10-231-9/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117206 91177308-0d34-0410-b5e6-96231b3b80d8
* my work on adding segment registers to LEA missed the Chris Lattner2010-07-131-12/+3
| | | | | | | | disassembler. Remove some code from the disassembler to compensate, unbreaking disassembly of lea's. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108226 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminated the classification of control registers into %ecr_Sean Callanan2010-05-061-2/+1
| | | | | | | | | | and %rcr_, leaving just %cr_ which is what people expect. Updated the disassembler to support this unified register set. Added a testcase to verify that the registers continue to be decoded correctly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103196 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a sign-extension bug in the X86 disassemblerSean Callanan2010-05-051-3/+55
| | | | | | | | | that was causing PC-relative branch targets to be evaluated incorrectly. Also added support for checking operand values to the llvm-mc tester. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103128 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a nasty layering violation in the edis sourceSean Callanan2010-04-131-0/+6
| | | | | | | | | | | | | | | | code. It used to #include the enhanced disassembly information for the targets it supported straight out of lib/Target/{X86,ARM,...} but now it uses a new interface provided by MCDisassembler, and (so far) implemented by X86 and ARM. Also removed hacky #define-controlled initialization of targets in edis. If clients only want edis to initialize a limited set of targets, they can set --enable-targets on the configure command line. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101179 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes to the X86 disassembler. The disassembler will nowSean Callanan2010-04-021-63/+96
| | | | | | | | return an error status in all failure cases, printing messages to debugs() only when debugging is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100229 91177308-0d34-0410-b5e6-96231b3b80d8
* TargetRegistry: Fix create{AsmInfo,MCDisassembler} to return non-const objects.Daniel Dunbar2010-03-201-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99097 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixes to the X86 disassembler:Sean Callanan2009-12-221-5/+16
| | | | | | | | | Made LEA memory operands emit only 4 MCInst operands. Made the scale operand equal 1 for instructions that have no SIB byte. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91919 91177308-0d34-0410-b5e6-96231b3b80d8
* Include based on the current path, since we already -I the X86 target's ↵Douglas Gregor2009-12-221-1/+1
| | | | | | path. Fixes CMake build git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91908 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed library dependencies between the X86 disassembler andSean Callanan2009-12-221-8/+5
| | | | | | | X86 codegen that were causing circular symbol dependencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91871 91177308-0d34-0410-b5e6-96231b3b80d8
* #if 0 out X86 disassembler for now, it is breaking the build in multiple places.Daniel Dunbar2009-12-191-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91778 91177308-0d34-0410-b5e6-96231b3b80d8
* Table-driven disassembler for the X86 architecture (16-, 32-, and 64-bit Sean Callanan2009-12-191-3/+435
| | | | | | | | | | | | | | | | | | | | | incarnations), integrated into the MC framework. The disassembler is table-driven, using a custom TableGen backend to generate hierarchical tables optimized for fast decode. The disassembler consumes MemoryObjects and produces arrays of MCInsts, adhering to the abstract base class MCDisassembler (llvm/MC/MCDisassembler.h). The disassembler is documented in detail in - lib/Target/X86/Disassembler/X86Disassembler.cpp (disassembler runtime) - utils/TableGen/DisassemblerEmitter.cpp (table emitter) You can test the disassembler by running llvm-mc -disassemble for i386 or x86_64 targets. Please let me know if you encounter any problems with it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91749 91177308-0d34-0410-b5e6-96231b3b80d8
* Sketch structure for X86 disassembler.Daniel Dunbar2009-11-251-0/+29
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89850 91177308-0d34-0410-b5e6-96231b3b80d8
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