aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/X86/X86FastISel.cpp
Commit message (Collapse)AuthorAgeFilesLines
* Rename PaddedSize to AllocSize, in the hope that thisDuncan Sands2009-05-091-2/+2
| | | | | | | | will make it more obvious what it represents, and stop it being confused with the StoreSize. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71349 91177308-0d34-0410-b5e6-96231b3b80d8
* X86FastISel doesn't support the -tailcallopt ABI.Dan Gohman2009-05-041-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70902 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,Dan Gohman2009-04-271-2/+2
| | | | | | | GR32_ABCD, and GR64_ABCD, respectively, to help describe them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70210 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement x86 h-register extract support.Dan Gohman2009-04-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | - Add patterns for h-register extract, which avoids a shift and mask, and in some cases a temporary register. - Add address-mode matching for turning (X>>(8-n))&(255<<n), where n is a valid address-mode scale value, into an h-register extract and a scaled-offset address. - Replace X86's MOV32to32_ and related instructions with the new target-independent COPY_TO_SUBREG instruction. On x86-64 there are complicated constraints on h registers, and CodeGen doesn't currently provide a high-level way to express all of them, so they are handled with a bunch of special code. This code currently only supports extracts where the result is used by a zero-extend or a store, though these are fairly common. These transformations are not always beneficial; since there are only 4 h registers, they sometimes require extra move instructions, and this sometimes increases register pressure because it can force out values that would otherwise be in one of those registers. However, this appears to be relatively uncommon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68962 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a cross-block fastisel crash handling overflow intrinsics.Chris Lattner2009-04-121-5/+16
| | | | | | | See comment for details. This fixes rdar://6772169 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68890 91177308-0d34-0410-b5e6-96231b3b80d8
* simplify code by using IntrinsicInst.Chris Lattner2009-04-121-69/+54
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68887 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new TargetInstrDesc::hasImplicitUseOfPhysReg andChris Lattner2009-04-121-15/+3
| | | | | | | | hasImplicitDefOfPhysReg methods. Use them to remove a look in X86 fast isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68886 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply 68552.Rafael Espindola2009-04-081-2/+2
| | | | | | | | Tested by bootstrapping llvm-gcc and using that to build llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert r68552. This was causing a failure in the self-hosting LLVMBill Wendling2009-04-071-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | builds. --- Reverse-merging (from foreign repository) r68552 into '.': U test/CodeGen/X86/tls8.ll U test/CodeGen/X86/tls10.ll U test/CodeGen/X86/tls2.ll U test/CodeGen/X86/tls6.ll U lib/Target/X86/X86Instr64bit.td U lib/Target/X86/X86InstrSSE.td U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86RegisterInfo.cpp U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86CodeEmitter.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86InstrInfo.h U lib/Target/X86/X86ISelDAGToDAG.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h U lib/Target/X86/X86ISelLowering.h U lib/Target/X86/X86InstrInfo.cpp U lib/Target/X86/X86InstrBuilder.h U lib/Target/X86/X86RegisterInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce code duplication on the TLS implementation.Rafael Espindola2009-04-071-2/+2
| | | | | | | | | | | | This introduces a small regression on the generated code quality in the case we are just computing addresses, not loading values. Will work on it and on X86-64 support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve FastISel's handling of truncates to i1, and implementDan Gohman2009-03-131-0/+13
| | | | | | | | | ptrtoint and inttoptr in X86FastISel. These casts aren't always handled in the generic FastISel code because X86 sometimes needs custom code to do truncation and zero-extension. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66988 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix FastISel's assumption that i1 values are always zero-extendedDan Gohman2009-03-131-2/+4
| | | | | | | | | | by inserting explicit zero extensions where necessary. Included is a testcase where SelectionDAG produces a virtual register holding an i1 value which FastISel previously mistakenly assumed to be zero-extended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66941 91177308-0d34-0410-b5e6-96231b3b80d8
* generalize this code so that fast isel handles integer truncates to i1, whichChris Lattner2009-03-131-2/+4
| | | | | | | | codegen to the same thing as integer truncates to i8 (the top bits are just undefined). This implements rdar://6667338 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66902 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some significant problems with constant pools that resulted in ↵Evan Cheng2009-03-131-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | unnecessary paddings between constant pool entries, larger than necessary alignments (e.g. 8 byte alignment for .literal4 sections), and potentially other issues. 1. ConstantPoolSDNode alignment field is log2 value of the alignment requirement. This is not consistent with other SDNode variants. 2. MachineConstantPool alignment field is also a log2 value. 3. However, some places are creating ConstantPoolSDNode with alignment value rather than log2 values. This creates entries with artificially large alignments, e.g. 256 for SSE vector values. 4. Constant pool entry offsets are computed when they are created. However, asm printer group them by sections. That means the offsets are no longer valid. However, asm printer uses them to determine size of padding between entries. 5. Asm printer uses expensive data structure multimap to track constant pool entries by sections. 6. Asm printer iterate over SmallPtrSet when it's emitting constant pool entries. This is non-deterministic. Solutions: 1. ConstantPoolSDNode alignment field is changed to keep non-log2 value. 2. MachineConstantPool alignment field is also changed to keep non-log2 value. 3. Functions that create ConstantPool nodes are passing in non-log2 alignments. 4. MachineConstantPoolEntry no longer keeps an offset field. It's replaced with an alignment field. Offsets are not computed when constant pool entries are created. They are computed on the fly in asm printer and JIT. 5. Asm printer uses cheaper data structure to group constant pool entries. 6. Asm printer compute entry offsets after grouping is done. 7. Change JIT code to compute entry offsets on the fly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66875 91177308-0d34-0410-b5e6-96231b3b80d8
* do not export all the X86FastISel symbols, ever.Chris Lattner2009-03-081-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66382 91177308-0d34-0410-b5e6-96231b3b80d8
* Fast-isel can't do TLS yet, so it should fall back to SDISelDan Gohman2009-02-231-0/+6
| | | | | | | if it sees TLS addresses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65341 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove non-DebugLoc versions of BuildMI from X86.Dale Johannesen2009-02-131-38/+41
| | | | | | | | There were some that might even matter in X86FastISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64437 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and ↵Evan Cheng2009-01-221-1/+2
| | | | | | SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62762 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-2/+2
| | | | | | sub-register indices as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
* Use DebugInfo interface to lower dbg_* intrinsics.Devang Patel2009-01-131-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62127 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename getABITypeSize to getTypePaddedSize, asDuncan Sands2009-01-121-2/+2
| | | | | | | suggested by Chris. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62099 91177308-0d34-0410-b5e6-96231b3b80d8
* X86_COND_C and X86_COND_NC are alternate mnemonics forDan Gohman2009-01-071-7/+7
| | | | | | | X86_COND_B and X86_COND_AE, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61835 91177308-0d34-0410-b5e6-96231b3b80d8
* Silence unused variable warnings.Devang Patel2008-12-231-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61392 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix fast-isel to not emit invalid assembly when presented with aDan Gohman2008-12-201-1/+1
| | | | | | | | constant shift count that doesn't fit in the shift instruction's immediate field. This fixes PR3242. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61281 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some release-assert warningsChris Lattner2008-12-191-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61244 91177308-0d34-0410-b5e6-96231b3b80d8
* Only perform SETO/SETC to JO/JC conversion if extractvalue is coming from an ↵Bill Wendling2008-12-101-35/+50
| | | | | | arithmetic with overflow instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60844 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement fast-isel conversion of a branch instruction that's branching on anBill Wendling2008-12-091-0/+63
| | | | | | | | | | overflow/carry from the "arithmetic with overflow" intrinsics. It searches the machine basic block from bottom to top to find the SETO/SETC instruction that is its conditional. If an instruction modifies EFLAGS before it reaches the SETO/SETC instruction, then it defaults to the normal instruction emission. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60807 91177308-0d34-0410-b5e6-96231b3b80d8
* Correct my English.Bill Wendling2008-12-091-8/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60753 91177308-0d34-0410-b5e6-96231b3b80d8
* Add initial support for fast-isel of the [SU]ADDO intrinsics. It isn'tBill Wendling2008-12-091-7/+84
| | | | | | | | | | | | | | | | | | | | complete. For instance, it lowers the common case into this less-than-optimal code: addl %ecx, %eax seto %cl testb %cl, %cl jne LBB1_2 ## overflow instead of: addl %ecx, %eax jo LBB1_2 ## overflow That will come in a future commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60737 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of mistaken switch case fall-throughs. Thanks to BillDan Gohman2008-12-081-0/+2
| | | | | | | for spotting these! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60728 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out the code for sign-extending/truncating gep indicesDan Gohman2008-12-081-3/+3
| | | | | | | | | | and use it in x86 address mode folding. Also, make getRegForValue return 0 for illegal types even if it has a ValueMap for them, because Argument values are put in the ValueMap. This fixes PR3181. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60696 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the optimized FCMP_OEQ/FCMP_UNE code for x86 fast-isel.Dan Gohman2008-10-211-0/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57915 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for folding immediates into stores when they Chris Lattner2008-10-151-20/+20
| | | | | | | | are due to argument passing in calls. This is significant because it hits all immediate arguments to calls on x86-32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57556 91177308-0d34-0410-b5e6-96231b3b80d8
* fold immediates into stores in simple cases, this produces diffs like Chris Lattner2008-10-151-30/+46
| | | | | | | | | | | | | this: - movl $0, %eax - movl %eax, _yy_n_chars + movl $0, _yy_n_chars git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57555 91177308-0d34-0410-b5e6-96231b3b80d8
* fold compare of null pointer into compare with 0.Chris Lattner2008-10-151-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57553 91177308-0d34-0410-b5e6-96231b3b80d8
* Some minor cleanups:Chris Lattner2008-10-151-40/+30
| | | | | | | | | | | | | | | 1. Compute action in X86SelectSelect based on MVT instead of type. 2. Use TLI.getValueType(..) instead of MVT::getVT(..) because the former handles pointers and the later doesn't. 3. Don't pass TLI into isTypeLegal, since it already has access to it as an ivar. #2 gives fast isel some minor new functionality: handling load/stores of pointers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57552 91177308-0d34-0410-b5e6-96231b3b80d8
* Use switch on VT instead of Type* comparisons.Chris Lattner2008-10-151-19/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57551 91177308-0d34-0410-b5e6-96231b3b80d8
* Use X86FastEmitCompare for FCMP_OEQ and FCMP_UNE: it doesn'tChris Lattner2008-10-151-17/+8
| | | | | | | change the generated code, but makes the code simpler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57550 91177308-0d34-0410-b5e6-96231b3b80d8
* refactor compare emission out into a new X86FastEmitCompare method,Chris Lattner2008-10-151-29/+49
| | | | | | | | | which makes it easy to share the compare/imm folding logic with 'setcc'. This shaves a bunch of instructions off the common select case, which happens a lot in llvm-gcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57549 91177308-0d34-0410-b5e6-96231b3b80d8
* Fold immediates into compares when possible, producing "cmp $4, %eax" instead ofChris Lattner2008-10-151-3/+36
| | | | | | | loading 4 into a register and then doing the compare. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57548 91177308-0d34-0410-b5e6-96231b3b80d8
* more minor refactoring of X86SelectBranch, no functionality change.Chris Lattner2008-10-151-13/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57547 91177308-0d34-0410-b5e6-96231b3b80d8
* factor buildmi calls in X86SelectBranchChris Lattner2008-10-151-89/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57546 91177308-0d34-0410-b5e6-96231b3b80d8
* factor some more BuildMI's in X86SelectCmpChris Lattner2008-10-151-92/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57545 91177308-0d34-0410-b5e6-96231b3b80d8
* factor some BuildMI calls, no functionality change.Chris Lattner2008-10-151-46/+56
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57544 91177308-0d34-0410-b5e6-96231b3b80d8
* FastISel support for exception-handling constructs.Dan Gohman2008-10-141-4/+20
| | | | | | | | | | - Move the EH landing-pad code and adjust it so that it works with FastISel as well as with SDISel. - Add FastISel support for @llvm.eh.exception and @llvm.eh.selector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57539 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MBB successors and physreg Uses in the same order thatDan Gohman2008-10-071-7/+4
| | | | | | | | SDISel typically adds them in. This makes it a little easier to compare FastISel output with SDISel output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57266 91177308-0d34-0410-b5e6-96231b3b80d8
* Instead of emitting an implicit use for the super-register ofDan Gohman2008-10-071-6/+10
| | | | | | | | | X86::CL that was used, emit an EXTRACT_SUBREG from the CL super-register to CL. This more precisely describes how the CL register is being used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57264 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix X86FastISel to handle dynamic allocas that have avoidedDan Gohman2008-10-031-0/+10
| | | | | | | | getting inserted into the ValueMap. This avoids infinite recursion in some rare cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56989 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimize conditional branches in X86FastISel. This replacesDan Gohman2008-10-021-16/+142
| | | | | | | | | | | | sequences like this: sete %al testb %al, %al jne LBB11_1 with this: je LBB11_1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56969 91177308-0d34-0410-b5e6-96231b3b80d8
* Work around an interaction between fast-isel and regalloc=local. TheDan Gohman2008-10-021-1/+5
| | | | | | | | | | | | | | | | | | local register allocator's physreg liveness doesn't recognize subregs, so it doesn't know that defs of %ecx that are immediately followed by uses of %cl aren't dead. This comes up due to the way fast-isel emits shift instructions. This is a temporary workaround. Arguably, local regalloc should handle subreg references correctly. On the other hand, perhaps fast-isel should use INSERT_SUBREG instead of just assigning to the most convenient super-register of %cl when lowering shifts. This fixes MultiSource/Benchmarks/MallocBench/espresso, MultiSource/Applications/hexxagon, and others, under -fast. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56947 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-07-03 07:35:32 +0000