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* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-65/+64
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update to LLVM 3.5a.Stephen Hines2014-04-241-47/+72
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* Add hadSideEffects=0 to some instructions.Craig Topper2013-09-031-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189779 91177308-0d34-0410-b5e6-96231b3b80d8
* Skip moving call address loading into callseq when targets prefer register ↵Michael Liao2013-03-281-2/+3
| | | | | | | | | | | | | | | | | | | | indirect call. To enable a load of a call address to be folded with that call, this load is moved from outside of callseq into callseq. Such a moving adds a non-glued node (that load) into a glued sequence. This non-glue load is only removed when DAG selection folds them into a memory form call instruction. When such instruction selection is disabled, it breaks DAG schedule. To prevent that, such moving is disabled when target favors register indirect call. Previous workaround disabling CALL32m/CALL64m insn selection is removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178308 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate control instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-261-28/+41
| | | | | | | This could definitely be more granular. I am not sure if it makes a difference. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178049 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark X86::RET and RETI instructions as variadic.Jakob Stoklund Olesen2012-08-241-2/+5
| | | | | | | There is special magic happening when returning floating point values on the x87 stack. The RET instructions get extra f80 operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162592 91177308-0d34-0410-b5e6-96231b3b80d8
* Make X86 call and return instructions non-variadic.Jakob Stoklund Olesen2012-07-041-24/+24
| | | | | | | Function argument and return value registers aren't part of the encoding, so they should be implicit operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159728 91177308-0d34-0410-b5e6-96231b3b80d8
* Use ptr_rc_tailcall instead of GR32_TC.Jakob Stoklund Olesen2012-05-091-2/+2
| | | | | | | | | The getPointerRegClass() hook will return GR32_TC, or whatever is appropriate for the current function. Patch by Yiannis Tsiouris! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156459 91177308-0d34-0410-b5e6-96231b3b80d8
* Add retw and lretw instructions. Also, fix Intel syntax parsing for allCharles Davis2012-04-111-5/+10
| | | | | | | ret instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by ↵Craig Topper2012-02-271-1/+1
| | | | | | Kay Tiong Khoo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151510 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the same CALL instructions for Windows as for everything else.Jakob Stoklund Olesen2012-02-161-47/+22
| | | | | | | The different calling conventions and call-preserved registers are represented with regmask operands that are added dynamically. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150708 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable register mask operands for x86 calls.Jakob Stoklund Olesen2012-02-161-27/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call instructions no longer have a list of 43 call-clobbered registers. Instead, they get a single register mask operand with a bit vector of call-preserved registers. This saves a lot of memory, 42 x 32 bytes = 1344 bytes per call instruction, and it speeds up building call instructions because those 43 imp-def operands no longer need to be added to use-def lists. (And removed and shifted and re-added for every explicit call operand). Passes like LiveVariables, LiveIntervals, RAGreedy, PEI, and BranchFolding are significantly faster because they can deal with call clobbers in bulk. Overall, clang -O2 is between 0% and 8% faster, uniformly distributed depending on call density in the compiled code. Debug builds using clang -O0 are 0% - 3% faster. I have verified that this patch doesn't change the assembly generated for the LLVM nightly test suite when building with -disable-copyprop and -disable-branch-fold. Branch folding behaves slightly differently in a few cases because call instructions have different hash values now. Copy propagation flushes its data structures when it crosses a register mask operand. This causes it to leave a few dead copies behind, on the order of 20 instruction across the entire nightly test suite, including SPEC. Fixing this properly would require the pass to use different data structures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150638 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-011-50/+56
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle call-clobbered ymm registers on Win64.Jakob Stoklund Olesen2012-01-261-1/+1
| | | | | | | | | | | | | | The Win64 calling convention has xmm6-15 as callee-saved while still clobbering all ymm registers. Add a YMM_HI_6_15 pseudo-register that aliases the clobbered part of the ymm registers, and mark that as call-clobbered. This allows live xmm registers across calls. This hack wouldn't be necessary with RegisterMask operands representing the call clobbers, but they are not quite operational yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149088 91177308-0d34-0410-b5e6-96231b3b80d8
* Intel syntax: For now, disable ambiguous JMP64pcrel32 for intel syntax.Devang Patel2012-01-201-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148569 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/X86: [PR8777][PR8778] Tweak alloca/chkstk for Windows targets.NAKAMURA Takumi2011-03-241-0/+10
| | | | | | FIXME: Some cleanups would be needed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128206 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/X86: Tweak win64's tailcall.NAKAMURA Takumi2011-01-261-6/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124272 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix whitespace.NAKAMURA Takumi2011-01-261-20/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124270 91177308-0d34-0410-b5e6-96231b3b80d8
* Use pushq / popq instead of subq $8, %rsp / addq $8, %rsp to adjust stack inEvan Cheng2011-01-031-1/+1
| | | | | | | | | | | | prologue and epilogue if the adjustment is 8. Similarly, use pushl / popl if the adjustment is 4 in 32-bit mode. In the epilogue, takes care to pop to a caller-saved register that's not live at the exit (either return or tailcall instruction). rdar://8771137 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122783 91177308-0d34-0410-b5e6-96231b3b80d8
* Migrate X86InstrControl.td to use PseudoI and fix a couple of 80-col violationsEric Christopher2010-11-301-19/+15
| | | | | | | while I'm in there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120466 91177308-0d34-0410-b5e6-96231b3b80d8
* accept lret as an alias for lretl, fixing the reopened part of PR8592Chris Lattner2010-11-121-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118916 91177308-0d34-0410-b5e6-96231b3b80d8
* implement PR8592: empirically "lretq" is a "lret" with a rex.w prefix.Chris Lattner2010-11-121-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118903 91177308-0d34-0410-b5e6-96231b3b80d8
* Added a handful of x86-32 instructions that were missing so that llvm-mc wouldKevin Enderby2010-10-181-0/+5
| | | | | | | | | | | be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
* continue moving stuff out to X86InstrSystem.td. MoveChris Lattner2010-10-051-0/+291
control flow stuff out to X86InstrControl.td. Move some compiler pseudo instructions and Pat<> patterns out to X86InstrCompiler.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115596 91177308-0d34-0410-b5e6-96231b3b80d8
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