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* Undo my brain cramp.Evan Cheng2009-07-101-6/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75290 91177308-0d34-0410-b5e6-96231b3b80d8
* CMOVxx doesn't swap operands which it's commuted.Evan Cheng2009-07-101-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75266 91177308-0d34-0410-b5e6-96231b3b80d8
* add a predicate to determine if a global var reference requires aChris Lattner2009-07-101-0/+16
| | | | | | | PIC-base to be added in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75238 91177308-0d34-0410-b5e6-96231b3b80d8
* change isGlobalStubReference to take target flags instead of a MachineOperand.Chris Lattner2009-07-101-6/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75236 91177308-0d34-0410-b5e6-96231b3b80d8
* add a new predicate method that says whether a GlobalValue Chris Lattner2009-07-101-1/+27
| | | | | | | | MachineOperand is a reference to a stub, not a reference to the global variable itself. Look no context needed! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75233 91177308-0d34-0410-b5e6-96231b3b80d8
* move reasoning about darwin $non_lazy_ptr stubs from asmprinter intoChris Lattner2009-07-091-0/+20
| | | | | | | isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75117 91177308-0d34-0410-b5e6-96231b3b80d8
* make isel decide whether to emit $stub's on darwin instead of asmprinter.Chris Lattner2009-07-091-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75107 91177308-0d34-0410-b5e6-96231b3b80d8
* move handling of dllimport linkage in isel, not in asmprinter.Chris Lattner2009-07-091-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75086 91177308-0d34-0410-b5e6-96231b3b80d8
* Move all the TLS processing logic into isel, don't do it in asmprinter at all.Chris Lattner2009-06-261-3/+61
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74327 91177308-0d34-0410-b5e6-96231b3b80d8
* start adding logic in isel to determine asm printer semantics, step N of M.Chris Lattner2009-06-261-1/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74246 91177308-0d34-0410-b5e6-96231b3b80d8
* Use target-specific machine operand flags to eliminate a gross hackChris Lattner2009-06-251-1/+12
| | | | | | | from the asmprinter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74184 91177308-0d34-0410-b5e6-96231b3b80d8
* Re-apply 68552.Rafael Espindola2009-04-081-2/+9
| | | | | | | | Tested by bootstrapping llvm-gcc and using that to build llvm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68645 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert r68552. This was causing a failure in the self-hosting LLVMBill Wendling2009-04-071-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | builds. --- Reverse-merging (from foreign repository) r68552 into '.': U test/CodeGen/X86/tls8.ll U test/CodeGen/X86/tls10.ll U test/CodeGen/X86/tls2.ll U test/CodeGen/X86/tls6.ll U lib/Target/X86/X86Instr64bit.td U lib/Target/X86/X86InstrSSE.td U lib/Target/X86/X86InstrInfo.td U lib/Target/X86/X86RegisterInfo.cpp U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86CodeEmitter.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86InstrInfo.h U lib/Target/X86/X86ISelDAGToDAG.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h U lib/Target/X86/X86ISelLowering.h U lib/Target/X86/X86InstrInfo.cpp U lib/Target/X86/X86InstrBuilder.h U lib/Target/X86/X86RegisterInfo.td git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
* Reduce code duplication on the TLS implementation.Rafael Espindola2009-04-071-2/+9
| | | | | | | | | | | | This introduces a small regression on the generated code quality in the case we are just computing addresses, not loading values. Will work on it and on X86-64 support. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68552 91177308-0d34-0410-b5e6-96231b3b80d8
* Have only one definition of X86AddrNumOperands.Rafael Espindola2009-03-281-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67949 91177308-0d34-0410-b5e6-96231b3b80d8
* Turns out AnalyzeBranch can modify the mbb being analyzed. This is a nastyEvan Cheng2009-02-091-1/+2
| | | | | | | | | suprise to some callers, e.g. register coalescer. For now, add an parameter that tells AnalyzeBranch whether it's safe to modify the mbb. A better solution is out there, but I don't have time to deal with it right now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64124 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getPointerRegClass from TargetInstrInfo to TargetRegisterInfo.Evan Cheng2009-02-061-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63938 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TargetInstrInfo::isSafeToMoveRegisterClassDefs. It returns true if it's ↵Evan Cheng2009-02-061-4/+3
| | | | | | safe to move an instruction which defines a value in the register class. Replace pre-splitting specific IgnoreRegisterClassBarriers with this new hook. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63936 91177308-0d34-0410-b5e6-96231b3b80d8
* Change TargetInstrInfo::isMoveInstr to return source and destination ↵Evan Cheng2009-01-201-5/+6
| | | | | | sub-register indices as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62600 91177308-0d34-0410-b5e6-96231b3b80d8
* X86_COND_C and X86_COND_NC are alternate mnemonics forDan Gohman2009-01-071-5/+3
| | | | | | | X86_COND_B and X86_COND_AE, respectively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61835 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up #includes, deleting a bunch of unnecessary #includes.Dan Gohman2009-01-051-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61715 91177308-0d34-0410-b5e6-96231b3b80d8
* Split foldMemoryOperand into public non-virtual and protected virtualDan Gohman2008-12-031-12/+12
| | | | | | | | parts, and add target-independent code to add/preserve MachineMemOperands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60488 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate something sensible for an [SU]ADDO op when the overflow/carry flag isBill Wendling2008-11-261-3/+5
| | | | | | | | | | | | | | | | | the conditional for the BRCOND statement. For instance, it will generate: addl %eax, %ecx jo LOF instead of addl %eax, %ecx ; About 10 instructions to compare the signs of LHS, RHS, and sum. jl LOF git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60123 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more const qualifiers. This fixes build breakage from r59540.Dan Gohman2008-11-181-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59542 91177308-0d34-0410-b5e6-96231b3b80d8
* For now, don't split live intervals around x87 stack register barriers. ↵Evan Cheng2008-10-271-0/+5
| | | | | | FpGET_ST0_80 must be right after a call instruction (and ADJCALLSTACKUP) so we need to find a way to prevent reload of x87 registers between them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58230 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimized FCMP_OEQ and FCMP_UNE for x86.Dan Gohman2008-10-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Where previously LLVM might emit code like this: ucomisd %xmm1, %xmm0 setne %al setp %cl orb %al, %cl jne .LBB4_2 it now emits this: ucomisd %xmm1, %xmm0 jne .LBB4_2 jp .LBB4_2 It has fewer instructions and uses fewer registers, but it does have more branches. And in the case that this code is followed by a non-fallthrough edge, it may be followed by a jmp instruction, resulting in three branch instructions in sequence. Some effort is made to avoid this situation. To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and FCMP_UNE in lowered form, and replace them with code that emits two branches, except in the case where it would require converting a fall-through edge to an explicit branch. Also, X86InstrInfo.cpp's branch analysis and transform code now knows now to handle blocks with multiple conditional branches. It uses loops instead of having fixed checks for up to two instructions. It can now analyze and transform code generated from FCMP_OEQ and FCMP_UNE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57873 91177308-0d34-0410-b5e6-96231b3b80d8
* getX86RegNum has long been moved to X86RegisterInfo.Evan Cheng2008-10-171-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57691 91177308-0d34-0410-b5e6-96231b3b80d8
* Const-ify several TargetInstrInfo methods.Dan Gohman2008-10-161-5/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57622 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ability to override segment (mostly for code emitter purposes).Anton Korobeynikov2008-10-111-1/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57380 91177308-0d34-0410-b5e6-96231b3b80d8
* Switch the MachineOperand accessors back to the short names likeDan Gohman2008-10-031-8/+8
| | | | | | | isReg, etc., from isRegister, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the GlobalBaseReg field out of X86ISelDAGToDAG.cppDan Gohman2008-09-301-3/+4
| | | | | | | | | and X86FastISel.cpp into X86MachineFunction.h, so that it can be shared, instead of having each selector keep track of its own. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56825 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the code for initializing the global base reg out ofDan Gohman2008-09-231-0/+5
| | | | | | | | X86ISelDAGToDAG.cpp and into X86InstrInfo.cpp. This will allow it to be reused by FastISel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56494 91177308-0d34-0410-b5e6-96231b3b80d8
* Backing out 55521. Not safe.Evan Cheng2008-08-291-5/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55548 91177308-0d34-0410-b5e6-96231b3b80d8
* Swap fp comparison operands and change predicate to allow load folding.Evan Cheng2008-08-281-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55521 91177308-0d34-0410-b5e6-96231b3b80d8
* Make TargetInstrInfo::copyRegToReg return a bool indicating whether the copy ↵Owen Anderson2008-08-261-1/+1
| | | | | | | | | | requested was inserted or not. This allows bitcast in fast isel to properly handle the case where an appropriate reg-to-reg copy is not available. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55375 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert uses of std::vector in TargetInstrInfo to SmallVector. This change ↵Owen Anderson2008-08-141-3/+4
| | | | | | had to be propoagated down into all the targets and up into all clients of this API. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54802 91177308-0d34-0410-b5e6-96231b3b80d8
* Pool-allocation for MachineInstrs, MachineBasicBlocks, andDan Gohman2008-07-071-3/+4
| | | | | | | | | | | | MachineMemOperands. The pools are owned by MachineFunctions. This drastically reduces the number of calls to malloc/free made during the "Emit" phase of scheduling, as well as later phases in CodeGen. Combined with other changes, this speeds up the "instruction selection" phase of CodeGen by 10% in some cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53212 91177308-0d34-0410-b5e6-96231b3b80d8
* Make LiveVariables even more optional, by making it optional in the call to ↵Owen Anderson2008-07-021-1/+1
| | | | | | | | | TargetInstrInfo::convertToThreeAddressInstruction Also, if LV isn't around, then TwoAddr doesn't need to be updating flags, since they won't have been set in the first place. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53058 91177308-0d34-0410-b5e6-96231b3b80d8
* Make intel asmprinter child of generic asmprinter, not x86 shared asm ↵Anton Korobeynikov2008-06-281-0/+17
| | | | | | printer. This leads to some code duplication, which will be resolved later. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52858 91177308-0d34-0410-b5e6-96231b3b80d8
* Add option to commuteInstruction() which forces it to create a new ↵Evan Cheng2008-06-161-1/+1
| | | | | | (commuted) instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52308 91177308-0d34-0410-b5e6-96231b3b80d8
* Change target-specific classes to use more precise static types.Dan Gohman2008-05-141-1/+1
| | | | | | | | This eliminates the need for several awkward casts, including the last dynamic_cast under lib/Target. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51091 91177308-0d34-0410-b5e6-96231b3b80d8
* Constify the machine instruction passed into theBill Wendling2008-05-121-1/+1
| | | | | | | "is{Trivially,Really}ReMaterializable" methods. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51001 91177308-0d34-0410-b5e6-96231b3b80d8
* Infrastructure for getting the machine code size of a function and an ↵Nicolas Geoffray2008-04-161-0/+15
| | | | | | instruction. X86, PowerPC and ARM are implemented git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49809 91177308-0d34-0410-b5e6-96231b3b80d8
* Move reMaterialize() from TargetRegisterInfo to TargetInstrInfo.Evan Cheng2008-03-311-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48995 91177308-0d34-0410-b5e6-96231b3b80d8
* Add explicit keywords.Dan Gohman2008-03-251-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48801 91177308-0d34-0410-b5e6-96231b3b80d8
* Get rid of a pseudo instruction and replace it with subreg based operation ↵Christopher Lamb2008-03-131-9/+1
| | | | | | | | | | on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48329 91177308-0d34-0410-b5e6-96231b3b80d8
* Recommitting parts of r48130. These do not appear to cause the observed ↵Christopher Lamb2008-03-111-0/+8
| | | | | | failures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48223 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests.Evan Cheng2008-03-101-8/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48167 91177308-0d34-0410-b5e6-96231b3b80d8
* Allow insert_subreg into implicit, target-specific values. Christopher Lamb2008-03-101-0/+8
| | | | | | | | Change insert/extract subreg instructions to be able to be used in TableGen patterns. Use the above features to reimplement an x86-64 pseudo instruction as a pattern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48130 91177308-0d34-0410-b5e6-96231b3b80d8
* Add lock prefix support to x86. Also add the instructions necessary for the ↵Andrew Lenharth2008-03-011-1/+5
| | | | | | atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47795 91177308-0d34-0410-b5e6-96231b3b80d8
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