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path: root/lib/Target/X86/X86InstrInfo.td
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* move sign and zero extensions out to their own file.Chris Lattner2010-10-051-88/+7
* move some instructions from Instr64Bit -> InstrInfo.Chris Lattner2010-10-051-12/+69
* move CMOV_FR32 and friends to InstrCompiler, since they are Chris Lattner2010-10-051-11/+5
* move various pattern matching support goop out of X86Instr64Bit, to liveChris Lattner2010-10-051-0/+58
* split conditional moves and setcc's out to their own file.Chris Lattner2010-10-051-635/+1
* move string pseudo instructions to InstrCompiler consolidate 64-bit and 32-bi...Chris Lattner2010-10-051-18/+5
* move the atomic pseudo instructions out to X86InstrCompiler.tdChris Lattner2010-10-051-237/+35
* move more pseudo instructions out to X86InstrCompiler.tdChris Lattner2010-10-051-105/+0
* move VMX instructions out to their own file.Chris Lattner2010-10-051-40/+2
* continue moving stuff out to X86InstrSystem.td. MoveChris Lattner2010-10-051-733/+9
* refactor .td files a bit, moving system instructions out to X86InstrSystem.tdChris Lattner2010-10-051-280/+9
* Implement support for the bizarre 3DNow! encoding (which is unlike anythingChris Lattner2010-10-031-0/+2
* stub out a header to put 3dNow! instructions into.Chris Lattner2010-10-021-0/+2
* Revert r114703 and r114702, removing the isConditionalMove flag from instruct...Owen Anderson2010-09-231-2/+2
* Add isConditionalMove bits to X86 and ARM instructions.Owen Anderson2010-09-231-2/+2
* Fix an inconsistency in the x86 backend that led it to reject "calll foo" onChris Lattner2010-09-221-3/+5
* reimplement elf TLS support in terms of addressing modes, eliminating Segment...Chris Lattner2010-09-221-4/+0
* give VZEXT_LOAD a memory operand, it now works with segment registers.Chris Lattner2010-09-221-2/+2
* reimplement support for GS and FS relative address space matchingChris Lattner2010-09-211-39/+6
* even though I'm about to rip it out, simplify the address mode stuffChris Lattner2010-09-211-24/+11
* fix rdar://8444631 - encoder crash on 'enter'Chris Lattner2010-09-171-2/+2
* fix the encoding of sldt GR16 to have the 0x66 prefix, andChris Lattner2010-09-151-1/+3
* fix bugs in push/pop segment support, rdar://8407242Chris Lattner2010-09-081-5/+35
* implement proper support for sysret{,l,q}, rdar://8403907Chris Lattner2010-09-081-2/+2
* implement the iret suite of instructions properly,Chris Lattner2010-09-081-2/+2
* fix the encoding of the "jump on *cx" family of instructions,Chris Lattner2010-09-081-4/+22
* Remove a dead comment.Evan Cheng2010-09-071-1/+0
* fix the operand constraints of the immediate form of in/out,Chris Lattner2010-09-061-6/+6
* Redefine LOOP* instructions from I to Ii8PCRel as they take an i8 argument.Roman Divacky2010-09-061-3/+3
* Don't call Predicate_* from X86 target.Jakob Stoklund Olesen2010-09-031-3/+1
* Fix nasty mingw32 bug, which e.g. prevented llvm-gcc bootstrap there.Anton Korobeynikov2010-08-251-3/+4
* Add a new llvm.x86.int intrinsic, allowing access to the Chris Lattner2010-08-231-3/+7
* fix PR7465, mishandling of lcall and ljmp: intersegment long Chris Lattner2010-08-191-12/+12
* Rework how the non-sse2 memory barrier is lowered so that theEric Christopher2010-08-141-8/+7
* Wording.Eric Christopher2010-08-091-1/+1
* Be a little bit more specific about target for the memory barrierEric Christopher2010-08-051-1/+2
* Make x86-64 membarriers work without sse and clean up some of theEric Christopher2010-08-041-2/+2
* Fix typo!Bruno Cardoso Lopes2010-07-301-8/+8
* Temporary hack to let codegen assert or generate poor code in caseBruno Cardoso Lopes2010-07-261-8/+13
* Add x86 CLMUL (Carry-less multiplication) cpu featureBruno Cardoso Lopes2010-07-231-0/+1
* Add complete assembler support for FMA3 instructions, with descriptions and e...Bruno Cardoso Lopes2010-07-231-0/+6
* Custom lower the memory barrier instructions and add supportEric Christopher2010-07-221-0/+29
* Pulling out previous patch, must've run the tests inEric Christopher2010-07-211-21/+0
* Lower MEMBARRIER on x86 and support processors without SSE2.Eric Christopher2010-07-211-0/+21
* Add 256-bit vaddsub, vhadd, vhsub, vblend and vdpp instructions!Bruno Cardoso Lopes2010-07-191-1/+1
* X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the sameDaniel Dunbar2010-07-191-2/+2
* X86: Mark some tail call pseduo instruction as code gen only.Daniel Dunbar2010-07-191-1/+2
* X86: Mark In32/64BitMode on LEAVE[64] and SYSEXIT[64].Daniel Dunbar2010-07-191-2/+2
* X86: Mark MOV.*_{TC,NOREX} instruction as code gen only, they aren't real.Daniel Dunbar2010-07-191-0/+4
* X86: MOV8o8a, MOV8ao8, etc. are only valid in 32-bit mode.Daniel Dunbar2010-07-191-6/+12