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* Update aosp/master LLVM for rebase to r230699.Stephen Hines2015-03-231-26/+62
| | | | Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
* Update aosp/master LLVM for rebase to r222494.Stephen Hines2014-12-021-9/+16
| | | | Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
* Update LLVM for 3.5 rebase (r209712).Stephen Hines2014-05-291-1/+7
| | | | Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
* Update to LLVM 3.5a.Stephen Hines2014-04-241-6/+6
| | | | Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
* Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-141-9/+10
| | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace a couple instructions with patterns referring to other instructions ↵Craig Topper2013-10-091-16/+11
| | | | | | with same encoding and operands. Mark a couple other instructions as CodeGenOnly since we have FR and VR instructions and only one of them is needed by the assembler/disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192274 91177308-0d34-0410-b5e6-96231b3b80d8
* Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. ↵Craig Topper2013-10-091-4/+4
| | | | | | This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192266 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unneeded MMX instruction definition by moving pattern to an ↵Craig Topper2013-10-081-6/+2
| | | | | | equivalent instruction definition and removing the filtering from the disassembler table building. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192175 91177308-0d34-0410-b5e6-96231b3b80d8
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-131-1/+1
| | | | | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX ↵Benjamin Kramer2013-06-141-7/+8
| | | | | | | | equivalent. Give it the right register format so we can also emit it when AVX is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183971 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply "Subtract isn't commutative, fix this for MMX psub." withEric Christopher2013-05-141-7/+7
| | | | | | | a somewhat randomly chosen cpu that will minimize cpu specific differences on bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181814 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporarily revert "Subtract isn't commutative, fix this for MMX psub."Eric Christopher2013-05-141-7/+7
| | | | | | It's causing failures on the atom bot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181812 91177308-0d34-0410-b5e6-96231b3b80d8
* Subtract isn't commutative, fix this for MMX psub.Eric Christopher2013-05-141-7/+7
| | | | | | Patch by Andrea DiBiagio. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181809 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate x87 and mmx instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-261-24/+52
| | | | | | | This only covers the instructions that were given itinerary classes for the Atom model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178050 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove IIC_DEFAULT from X86Schedule.tdJakob Stoklund Olesen2013-03-251-2/+2
| | | | | | | | All the instructions tagged with IIC_DEFAULT had nothing in common, and we already have a NoItineraries class to represent untagged instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177937 91177308-0d34-0410-b5e6-96231b3b80d8
* X86 MMX: optimize transfer from mmx to i32Manman Ren2012-10-301-2/+8
| | | | | | | | | | We used to generate a store (movq) + a load. Now we use movd. rdar://9946746 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167056 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce 'UseSSEx' to force SSE legacy encodingMichael Liao2012-08-301-32/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add 'UseSSEx' to force SSE legacy insn not being selected when AVX is enabled. As the penalty of inter-mixing SSE and AVX instructions, we need prevent SSE legacy insn from being generated except explicitly specified through some intrinsics. For patterns supported by both SSE and AVX, so far, we force AVX insn will be tried first relying on AddedComplexity or position in td file. It's error-prone and introduces bugs accidentally. 'UseSSEx' is disabled when AVX is turned on. For SSE insns inherited by AVX, we need this predicate to force VEX encoding or SSE legacy encoding only. For insns not inherited by AVX, we still use the previous predicates, i.e. 'HasSSEx'. So far, these insns fall into the following categories: * SSE insns with MMX operands * SSE insns with GPR/MEM operands only (xFENCE, PREFETCH, CLFLUSH, CRC, and etc.) * SSE4A insns. * MMX insns. * x87 insns added by SSE. 2 test cases are modified: - test/CodeGen/X86/fast-isel-x86-64.ll AVX code generation is different from SSE one. 'vcvtsi2sdq' cannot be selected by fast-isel due to complicated pattern and fast-isel fallback to materialize it from constant pool. - test/CodeGen/X86/widen_load-1.ll AVX code generation is different from SSE one after fixing SSE/AVX inter-mixing. Exec-domain fixing prefers 'vmovapd' instead of 'vmovaps'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162919 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the LowerMMXCONCAT_VECTORS function. It could never execute because ↵Craig Topper2012-08-131-14/+0
| | | | | | there are no legal 64-bit vector types that could be used as inputs to a 128-bit concat_vectors. Remove a target specific SDNode and its patterns that become unused as a result. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161742 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1.Craig Topper2012-07-301-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160941 91177308-0d34-0410-b5e6-96231b3b80d8
* Added X86 Atom latencies to X86InstrMMX.td.Preston Gurd2012-05-111-129/+274
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156615 91177308-0d34-0410-b5e6-96231b3b80d8
* Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, ↵Jia Liu2012-02-181-1/+1
| | | | | | MSP430, PPC, PTX, Sparc, X86, XCore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-011-4/+8
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction selection priority fixes to remove the XMM/XMMInt/orAVX ↵Craig Topper2012-01-101-20/+20
| | | | | | predicates. Another commit will remove orAVX functions from X86SubTarget. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147841 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't disable MMX support when AVX is enabled. Fix predicates for MMX ↵Craig Topper2012-01-091-24/+24
| | | | | | instructions that were added along with SSE instructions to check for AVX in addition to SSE level. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147762 91177308-0d34-0410-b5e6-96231b3b80d8
* PR9848: pandn is not commutative.Eli Friedman2011-05-051-1/+1
| | | | | | | | No test because I can't think of any way to write one that won't break quickly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130932 91177308-0d34-0410-b5e6-96231b3b80d8
* The pshufw instruction came about in MMX2 when SSE was introduced. Don't placeBill Wendling2010-10-041-3/+3
| | | | | | | | | | it in with the SSSE3 instructions. Steward! Could you place this chair by the aft sun deck? I'm trying to get away from the Astors. They are such boors! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115552 91177308-0d34-0410-b5e6-96231b3b80d8
* the immediate field of pshufw is actually an 8-bit field, not a 8-bit field ↵Chris Lattner2010-10-031-2/+2
| | | | | | that is sign extended. This fixes PR8288 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115473 91177308-0d34-0410-b5e6-96231b3b80d8
* add support for the prefetch/prefetchw instructions, move femms intoChris Lattner2010-10-031-3/+1
| | | | | | | | the right file. The assembler supports all the 3dnow instructions now, but not the "3dnowa" ones. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115468 91177308-0d34-0410-b5e6-96231b3b80d8
* stub out a header to put 3dNow! instructions into.Chris Lattner2010-10-021-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115429 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a regression introduced in r115243, in which the instructionChris Lattner2010-10-021-0/+16
| | | | | | | backing int_x86_ssse3_pshuf_w got removed. This caused PR8280. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115422 91177308-0d34-0410-b5e6-96231b3b80d8
* Massive rewrite of MMX: Dale Johannesen2010-09-301-493/+69
| | | | | | | | | | | | | | | | | | | | | The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115243 91177308-0d34-0410-b5e6-96231b3b80d8
* Move remaining MMX instructions from SSE to MMX.Dale Johannesen2010-09-091-62/+44
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113501 91177308-0d34-0410-b5e6-96231b3b80d8
* Move most MMX instructions (defined as anything thatDale Johannesen2010-09-091-1/+120
| | | | | | | | | uses MMX, even if it also uses other things) from InstrSSE into InstrMMX. No (intended) functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113462 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsic-based patterns for MMX PINSRW and PEXTRW.Dale Johannesen2010-09-081-0/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113420 91177308-0d34-0410-b5e6-96231b3b80d8
* Slight cleanup, use only one form of MMXI_binop_rm_int.Dale Johannesen2010-09-081-53/+37
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113406 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsic forms of mmx<->sse conversions. Notes:Dale Johannesen2010-09-081-0/+51
| | | | | | | | | | | Omission of memory form of PI2PD is intentional; this does not use an MMX register and does not put the chip into MMX mode (PI2PS, oddly enough, does). Operands of PI2PS follow the gcc builtin, not Intel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113388 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns for MMX that use the new intrinsics.Dale Johannesen2010-09-071-14/+60
| | | | | | | | | Enable palignr intrinsic. These may need adjustment for a new VT in due course. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113233 91177308-0d34-0410-b5e6-96231b3b80d8
* fix the encoding of MMX_MOVFR642Qrr, it starts with 0xF2 not 0xF3,Chris Lattner2010-07-151-1/+1
| | | | | | | | | this fixes rdar://8192860. Unfortunately it can only be triggered with llc because llvm-mc matches another (correctly encoded) version of this, so no testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108454 91177308-0d34-0410-b5e6-96231b3b80d8
* rip out even more sporadic v2f32 support.Chris Lattner2010-07-051-14/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107610 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an mmx movd encoding.Dan Gohman2010-05-241-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104552 91177308-0d34-0410-b5e6-96231b3b80d8
* Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn'tDan Gohman2010-05-201-3/+0
| | | | | | | have a pattern and it had an invalid encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104244 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed the encoding of two of the X86 movq instuctions. The Move quadword fromKevin Enderby2010-05-031-1/+1
| | | | | | | | mm to mm/m64 and the Move quadword from xmm2/mem64 to xmm1 had the incorrect encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102952 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some missing x86 patterns for movdq2q. Fixes two (LLVM-)GCC DejaGNU ↵Stuart Hastings2010-04-231-0/+11
| | | | | | testcases. Radar 6881029. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102199 91177308-0d34-0410-b5e6-96231b3b80d8
* remove a bunch of dead patterns.Chris Lattner2010-03-281-13/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99748 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a few more ambiguous types.Chris Lattner2010-03-151-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98531 91177308-0d34-0410-b5e6-96231b3b80d8
* fix some more ambiguous patterns, remove another nontemporalstoreChris Lattner2010-03-081-4/+5
| | | | | | | pattern which is broken (source and address swapped). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97958 91177308-0d34-0410-b5e6-96231b3b80d8
* The mayHaveSideEffects flag is no longer used.Dan Gohman2010-02-271-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97348 91177308-0d34-0410-b5e6-96231b3b80d8
* remove a confused pattern that is trying to match an addressChris Lattner2010-02-231-7/+0
| | | | | | | then use it as an MMX register (!?). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96901 91177308-0d34-0410-b5e6-96231b3b80d8
* X86InstrInfoSSE.td declares PINSRW as having type v8i16,Chris Lattner2010-02-231-3/+5
| | | | | | | | don't alis it in the MMX .td file with a different width, split into two X86ISD opcodes. This fixes an x86 testcase. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96859 91177308-0d34-0410-b5e6-96231b3b80d8
* TableGen fragment refactoring.David Greene2010-02-091-50/+0
| | | | | | | | | | Move some utility TableGen defs, classes, etc. into a common file so they may be used my multiple pattern files. We will use this for the AVX specification to help with the transition from the current SSE specification. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95727 91177308-0d34-0410-b5e6-96231b3b80d8
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