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* X86: Turn fp selects into mask operations.Benjamin Kramer2013-08-041-2/+2
| | | | | | | | | | | | | | | | | | | | | | | double test(double a, double b, double c, double d) { return a<b ? c : d; } before: _test: ucomisd %xmm0, %xmm1 ja LBB0_2 movaps %xmm3, %xmm2 LBB0_2: movaps %xmm2, %xmm0 after: _test: cmpltsd %xmm1, %xmm0 andpd %xmm0, %xmm2 andnpd %xmm3, %xmm0 orpd %xmm2, %xmm0 Small speedup on Benchmarks/SmallPT git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187706 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512 set: added VEXTRACTPS instructionElena Demikhovsky2013-08-041-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187705 91177308-0d34-0410-b5e6-96231b3b80d8
* Added INSERT and EXTRACT intructions from AVX-512 ISA.Elena Demikhovsky2013-07-311-80/+80
| | | | | | | | | | All insertf*/extractf* functions replaced with insert/extract since we have insertf and inserti forms. Added lowering for INSERT_VECTOR_ELT / EXTRACT_VECTOR_ELT for 512-bit vectors. Added lowering for EXTRACT/INSERT subvector for 512-bit vectors. Added a test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187491 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed register names (and pointer keywords) to be lower case when using ↵Craig Topper2013-07-311-10/+10
| | | | | | | | | | Intel X86 assembler syntax. Patch by Richard Mitton. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187476 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some errant space charcters in mnemonic strings.Craig Topper2013-07-231-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186932 91177308-0d34-0410-b5e6-96231b3b80d8
* More Intel syntax alias fixes.Craig Topper2013-07-221-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186814 91177308-0d34-0410-b5e6-96231b3b80d8
* Change %xmm0 to XMM0 in Intel side of asm strings for PBLENDVB.Craig Topper2013-07-221-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186812 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed PackedDouble domain from scalar instructions. Added more formats for ↵Elena Demikhovsky2013-06-091-39/+39
| | | | | | the scalar stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183626 91177308-0d34-0410-b5e6-96231b3b80d8
* [PATCH] Fix VGATHER* operand constraintsMichael Liao2013-06-051-1/+3
| | | | | | | | | | | | | | Add earlyclobber constaints to prevent input register being allocated as the output register because, according to Intel spec [1], "If any pair of the index, mask, or destination registers are the same, this instruction results a UD fault." --- [1] http://software.intel.com/sites/default/files/319433-014.pdf git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183327 91177308-0d34-0410-b5e6-96231b3b80d8
* Removed SSEPacked domain from all forms (AVX, SSE, signed, unsigned) scalar ↵Elena Demikhovsky2013-05-211-24/+21
| | | | | | | | | compare instructions, like COMISS, COMISD. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182371 91177308-0d34-0410-b5e6-96231b3b80d8
* Corrected Atom latencies for SSE SQRT instructions.Preston Gurd2013-05-071-11/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181346 91177308-0d34-0410-b5e6-96231b3b80d8
* Put VMOVPQIto64rr in the VRPDI class.Rafael Espindola2013-05-011-3/+3
| | | | | | Patch by Joshua Magee. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180842 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Now that we have a canonical form for vector integer abs, match it into ↵Benjamin Kramer2013-04-261-0/+51
| | | | | | pabs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180600 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate the remaining x86 instructions with SchedRW lists.Jakob Stoklund Olesen2013-03-261-4/+4
| | | | | | | | | | Now all x86 instructions that have itinerary classes also have SchedRW lists. This is required before the new scheduling models can be used. There are still unannotated instructions remaining, but they don't have itinerary classes either. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178051 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove IIC_DEFAULT from X86Schedule.tdJakob Stoklund Olesen2013-03-251-4/+4
| | | | | | | | All the instructions tagged with IIC_DEFAULT had nothing in common, and we already have a NoItineraries class to represent untagged instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177937 91177308-0d34-0410-b5e6-96231b3b80d8
* Model prefetches and barriers as loads.Jakob Stoklund Olesen2013-03-201-1/+4
| | | | | | It's not yet clear if these instructions need a more careful model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177599 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a catch-all WriteSystem SchedWrite type.Jakob Stoklund Olesen2013-03-201-0/+2
| | | | | | This is used for all the expensive system instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177598 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate the remaining SSE MOV instructions.Jakob Stoklund Olesen2013-03-201-25/+45
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177592 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate SSE horizontal and integer instructions.Jakob Stoklund Olesen2013-03-201-16/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177591 91177308-0d34-0410-b5e6-96231b3b80d8
* Add some missing SSE annotations.Jakob Stoklund Olesen2013-03-201-8/+18
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177540 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate various null idioms with SchedRW lists.Jakob Stoklund Olesen2013-03-191-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177461 91177308-0d34-0410-b5e6-96231b3b80d8
* Annotate SSE float conversions with SchedRW lists.Jakob Stoklund Olesen2013-03-191-60/+81
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177460 91177308-0d34-0410-b5e6-96231b3b80d8
* Add SchedRW annotations to most of X86InstrSSE.td.Jakob Stoklund Olesen2013-03-181-186/+280
| | | | | | | | | | We hitch a ride with the existing OpndItins class that was used to add instruction itinerary classes in the many multiclasses in this file. Use the link provided by the X86FoldableSchedWrite.Folded to find the right SchedWrite for folded loads. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177326 91177308-0d34-0410-b5e6-96231b3b80d8
* Unaligned loads should use the VMOVUPS opcode.Nadav Rotem2013-03-141-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177130 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix inconsistent usage of PALIGN and PALIGNR when referring to the same ↵Craig Topper2013-01-281-17/+17
| | | | | | instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173667 91177308-0d34-0410-b5e6-96231b3b80d8
* Combine AVX and SSE forms of MOVSS and MOVSD into the same multiclasses so ↵Craig Topper2013-01-171-74/+50
| | | | | | they get instantiated together. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172704 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify nested strconcats in X86 td files since strconcat can take more ↵Craig Topper2013-01-141-25/+25
| | | | | | than 2 arguments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172379 91177308-0d34-0410-b5e6-96231b3b80d8
* Create a single multiclass for SSE and AVX version of MOVL/MOVH. Prevents ↵Craig Topper2013-01-141-23/+24
| | | | | | needing to specify everything twice. No functional change intended git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172378 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Add patterns for X86ISD::VSEXT in registers.Benjamin Kramer2013-01-131-0/+42
| | | | | | | Those can occur when something between the sextload and the store is on the same chain and blocks isel. Fixes PR14887. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172353 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary # tokens at the beginning and end of defm names.Craig Topper2013-01-071-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171694 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, ↵Craig Topper2013-01-061-27/+100
| | | | | | | | | | | | | cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior. cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix. cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix. Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171668 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, ↵Craig Topper2013-01-021-82/+97
| | | | | | and RCP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171356 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge SSE and AVX instruction definitions for PSHUFD/PSHUFHW/PSHUFLW.Craig Topper2013-01-021-62/+61
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171355 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert 171351. It broke MC/X86/x86-32-avx.s.Rafael Espindola2013-01-021-97/+82
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171352 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, ↵Craig Topper2013-01-011-82/+97
| | | | | | and RCP. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171351 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused argument from a multiclass.Craig Topper2013-01-011-5/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171340 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge intrinsic instruction definitions for SSE and AVX versions of RCPPS ↵Craig Topper2013-01-011-30/+34
| | | | | | and RSQRTPS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171339 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove 2 unused multiclasses.Craig Topper2013-01-011-26/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171338 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge AVX/SSE instruction definitions for SQRTPS/PD, RSQRTPS, RCPPS. No ↵Craig Topper2013-01-011-47/+58
| | | | | | funcitonal change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171337 91177308-0d34-0410-b5e6-96231b3b80d8
* Use packed instead of scalar itineraries for SSE1/2 SQRTPS/PD, RCPPS, and ↵Craig Topper2012-12-311-6/+6
| | | | | | RSQRTPS. VEX-encoded forms already use packed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171336 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to ↵Craig Topper2012-12-291-11/+1
| | | | | | target-independent ISD nodes and use the existing patterns for those. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171237 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove intrinsic specific instructions for SSE/SSE2/AVX floating point ↵Craig Topper2012-12-291-54/+0
| | | | | | max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171227 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses.Craig Topper2012-12-271-28/+28
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171171 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses.Craig Topper2012-12-271-49/+41
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171166 91177308-0d34-0410-b5e6-96231b3b80d8
* Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT.Craig Topper2012-12-271-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171143 91177308-0d34-0410-b5e6-96231b3b80d8
* Move single letter 'P' prefix out of multiclass now that tablegen allows ↵Craig Topper2012-12-271-86/+85
| | | | | | defm to start with #NAME. This makes instruction names more searchable again. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171141 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark all the _REV instructions as not having side effects. They aren't ↵Craig Topper2012-12-261-6/+6
| | | | | | really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171118 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a special conditional setting of neverHasSideEffects if the ↵Craig Topper2012-12-261-4/+3
| | | | | | instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171117 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge still more SSE/AVX instruction definitions.Craig Topper2012-12-261-43/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171103 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge more SSE/AVX instruction definitions.Craig Topper2012-12-261-129/+49
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171102 91177308-0d34-0410-b5e6-96231b3b80d8
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