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* More refactoring.Evan Cheng2011-07-251-1055/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135939 91177308-0d34-0410-b5e6-96231b3b80d8
* Refactor X86 target to separate MC code from Target code.Evan Cheng2011-07-251-20/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135930 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.Eli Friedman2011-07-201-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135607 91177308-0d34-0410-b5e6-96231b3b80d8
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-181-1/+1
| | | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-141-3/+0
| | | | | | | registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
* - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfoEvan Cheng2011-07-111-21/+24
| | | | | | | | | | | | | and MCSubtargetInfo. - Added methods to update subtarget features (used when targets automatically detect subtarget features or switch modes). - Teach X86Subtarget to update MCSubtargetInfo features bits since the MCSubtargetInfo layer can be shared with other modules. - These fixes .code 16 / .code 32 support since mode switch is updated in MCSubtargetInfo so MC code emitter can do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-281-9/+9
| | | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134021 91177308-0d34-0410-b5e6-96231b3b80d8
* ADD64ri32 sign extends its argument, so we need to use a R_X86_64_32S.Rafael Espindola2011-05-191-1/+2
| | | | | | | | Fixes PR9934. We really need to start tblgening the relocation info :-( git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131669 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a ton of comment typos found by codespell. Patch byChris Lattner2011-04-151-1/+1
| | | | | | | | Luis Felipe Strano Moraes! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129558 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the VIA PadLock instructions.Joerg Sonnenberger2011-04-041-0/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128826 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand Op0Mask by one bit in preparation for the PadLock prefixes.Joerg Sonnenberger2011-04-041-9/+9
| | | | | | | | | Define most shift masks incrementally to reduce the redundant hard-coding. Introduce new shift for the VEX flags to replace the magic constant 32 in various places. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128822 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement xgetbv and xsetbv.Rafael Espindola2011-02-221-0/+8
| | | | | | Patch by Jai Menon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126165 91177308-0d34-0410-b5e6-96231b3b80d8
* Make pushq produce signed relocations.Rafael Espindola2010-12-161-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122005 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Move target specific fixup info descriptors to TargetAsmBackend instead ofDaniel Dunbar2010-12-161-20/+0
| | | | | | | the MCCodeEmitter, which seems like a better organization. - Also, cleaned up some magic constants while in the area. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121953 91177308-0d34-0410-b5e6-96231b3b80d8
* Define generic 1, 2 and 4 byte pc relative relocations. They are commonRafael Espindola2010-11-281-16/+7
| | | | | | and at least the 4 byte one will be needed to implement the .cfi_* directives. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120240 91177308-0d34-0410-b5e6-96231b3b80d8
* Produce a relocation for pcrel absolute values. Based on a patch by David Meyer.Rafael Espindola2010-11-231-8/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120006 91177308-0d34-0410-b5e6-96231b3b80d8
* add fields to the .td files unconditionally, simplifying tblgen a bit.Chris Lattner2010-11-151-1/+1
| | | | | | | | Switch the ARM backend to use 'let' instead of 'set' with this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119120 91177308-0d34-0410-b5e6-96231b3b80d8
* Add X86::reloc_global_offset_table and use it to have a single place whereRafael Espindola2010-10-241-5/+6
| | | | | | we check for _GLOBAL_OFFSET_TABLE_. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117241 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle _GLOBAL_OFFSET_TABLE_ correctly.Rafael Espindola2010-10-201-0/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116932 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions.Jakob Stoklund Olesen2010-10-121-2/+1
| | | | | | | | | | | The reg-reg copies were no longer being generated since copyPhysReg copies physical registers only. The loads and stores are not necessary - The TC constraint is imposed by the TAILJMP and TCRETURN instructions, there should be no need for constrained loads and stores. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116314 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement support for the bizarre 3DNow! encoding (which is unlike anythingChris Lattner2010-10-031-0/+9
| | | | | | | | | | | | | else in X86), and add support for pavgusb. This is apparently the only instruction (other than movsx) that is preventing ffmpeg from building with clang. If someone else is interested in banging out the rest of the 3DNow! instructions, it should be quite easy now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115466 91177308-0d34-0410-b5e6-96231b3b80d8
* Correctly produce R_X86_64_32 or R_X86_64_32S.Rafael Espindola2010-09-301-6/+15
| | | | | | | | | | | | | With this patch in movq $foo, foo(%rip) foo: .long foo We produce a R_X86_64_32S for the first relocation and R_X86_64_32 for the second one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115134 91177308-0d34-0410-b5e6-96231b3b80d8
* Add parens to fix GCC warning:Nick Lewycky2010-09-291-2/+2
| | | | | | | lib/Target/X86/X86MCCodeEmitter.cpp: 190: error: suggest parentheses around '&&' within '||' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115064 91177308-0d34-0410-b5e6-96231b3b80d8
* make the x86 mccode emitter emit the 0x67 and 0x66 prefix bytes in the sameChris Lattner2010-09-291-4/+4
| | | | | | | order as cctools for diffability. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115022 91177308-0d34-0410-b5e6-96231b3b80d8
* implement support for 32-bit address operands in 64-bit mode, which Chris Lattner2010-09-291-5/+18
| | | | | | | are defined to emit the 0x67 prefix byte. rdar://8482675 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115021 91177308-0d34-0410-b5e6-96231b3b80d8
* fix rdar://8444631 - encoder crash on 'enter'Chris Lattner2010-09-171-0/+7
| | | | | | | What a weird instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114190 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR7748 without using microsoft extensionsBruno Cardoso Lopes2010-08-261-7/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112128 91177308-0d34-0410-b5e6-96231b3b80d8
* fix PR7465, mishandling of lcall and ljmp: intersegment long Chris Lattner2010-08-191-0/+8
| | | | | | | call and jumps. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111496 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r111082. No warnings for this common pattern.Argyrios Kyrtzidis2010-08-151-3/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111102 91177308-0d34-0410-b5e6-96231b3b80d8
* Add ATTRIBUTE_UNUSED to methods that are not supposed to be used.Argyrios Kyrtzidis2010-08-141-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111082 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX only vzeroall and vzeroupper instructionsBruno Cardoso Lopes2010-07-211-2/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109002 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new AVX vmaskmov instructions, and also fix the VEX encoding bits to ↵Bruno Cardoso Lopes2010-07-211-9/+20
| | | | | | support it git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108983 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX 256-bit conversion instructionsBruno Cardoso Lopes2010-07-131-0/+3
| | | | | | | Add the x86 VEX_L form to handle special cases where VEX_L must be set. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108274 91177308-0d34-0410-b5e6-96231b3b80d8
* Start the support for AVX instructions with 256-bit %ymm registers. A couple ofBruno Cardoso Lopes2010-07-091-1/+11
| | | | | | | | | | | | | | | | | notes: - The instructions are being added with dummy placeholder patterns using some 256 specifiers, this is not meant to work now, but since there are some multiclasses generic enough to accept them, when we go for codegen, the stuff will be already there. - Add VEX encoding bits to support YMM - Add MOVUPS and MOVAPS in the first round - Use "Y" as suffix for those Instructions: MOVUPSYrr, ... - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107996 91177308-0d34-0410-b5e6-96231b3b80d8
* Merge VEX enums with other x86 enum forms. Also fix all checks of which VEXBruno Cardoso Lopes2010-07-091-6/+6
| | | | | | | fields to use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107952 91177308-0d34-0410-b5e6-96231b3b80d8
* Factor out x86 segment override prefix encoding, and also use it for VEXBruno Cardoso Lopes2010-07-091-18/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107942 91177308-0d34-0410-b5e6-96231b3b80d8
* reject pseudo instructions early in the encoder.Chris Lattner2010-07-091-10/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107939 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing whitespaces from fileBruno Cardoso Lopes2010-07-091-66/+66
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107937 91177308-0d34-0410-b5e6-96231b3b80d8
* Change LEA to have 5 operands for its memory operand, justChris Lattner2010-07-081-9/+1
| | | | | | | | | | | | like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107934 91177308-0d34-0410-b5e6-96231b3b80d8
* add some long-overdue enums to refer to the parts of the 5-operandChris Lattner2010-07-081-7/+7
| | | | | | | | X86 memory operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107925 91177308-0d34-0410-b5e6-96231b3b80d8
* Rework segment prefix emission code to handle segmentsChris Lattner2010-07-081-47/+41
| | | | | | | | | | | | | in memory operands at the same type as hard coded segments. This fixes problems where we'd emit the segment override after the REX prefix on instructions like: mov %gs:(%rdi), %rax This fixes rdar://8127102. I have several cleanup patches coming next. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107917 91177308-0d34-0410-b5e6-96231b3b80d8
* finish up support for callw: PR7195Chris Lattner2010-07-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107826 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement the major chunk of PR7195: support for 'callw'Chris Lattner2010-07-071-2/+5
| | | | | | | | | in the integrated assembler. Still some discussion to be done. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107825 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix comment from previous patchBruno Cardoso Lopes2010-07-061-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107717 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX vblendvpd, vblendvps and vpblendvb instructionsBruno Cardoso Lopes2010-07-061-5/+23
| | | | | | | Update VEX encoding to support those new instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107715 91177308-0d34-0410-b5e6-96231b3b80d8
* indentationChris Lattner2010-07-041-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107599 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add support for the rest of AVX SSE3 instructionsBruno Cardoso Lopes2010-07-021-1/+1
| | | | | | | | | - Fix VEX prefix to be emitted with 3 bytes whenever VEX_5M represents a REX equivalent two byte leading opcode git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107523 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add AVX SSE2 Move doubleword and quadword instructions.Bruno Cardoso Lopes2010-07-011-5/+13
| | | | | | | | | | - Add encode bits for VEX_W - All 128-bit SSE 1 & SSE2 instructions that are described in the .td file now have a AVX encoded form already working. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107365 91177308-0d34-0410-b5e6-96231b3b80d8
* - Add AVX form of all SSE2 logical instructionsBruno Cardoso Lopes2010-06-301-22/+37
| | | | | | | - Add VEX encoding bits to x86 MRM0r-MRM7r git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107238 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX ld/st XCSR register.Bruno Cardoso Lopes2010-06-291-5/+7
| | | | | | | | Add VEX encoding bits for MRMXm x86 form git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107204 91177308-0d34-0410-b5e6-96231b3b80d8
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