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* Prevent extra calls to ToggleFeature for Feature64Bit and FeatureCMOV if ↵Craig Topper2013-09-181-2/+2
| | | | | | they've already been enabled. The extra call ends up clearing the bit in FeatureBits since its a 'toggle'. Can't prove that anything was broken because of this since I don't think the FeatureBits for these are used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190920 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix X86 subtarget to not overwrite the autodetected features by calling ↵Craig Topper2013-09-181-1/+1
| | | | | | InitMCProcessorInfo right after detecting them. Instead add a new function that only updates the scheduling model and call that. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190919 91177308-0d34-0410-b5e6-96231b3b80d8
* Lift alignment restrictions for load/store folding on ↵Craig Topper2013-09-181-10/+10
| | | | | | VINSERTF128/VEXTRACTF128. Fixes PR17268. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190916 91177308-0d34-0410-b5e6-96231b3b80d8
* COFF: Ensure that objects produced by LLVM link with /safesehReid Kleckner2013-09-171-0/+20
| | | | | | | | | | | | | | | | | | | | Summary: We indicate that the object files are safe by emitting a @feat.00 absolute address symbol. The address is presumably interpreted as a bitfield of features that the compiler would like to enable. Bit 0 is documented in the PE COFF spec to opt in to "registered SEH", which is what /safeseh enables. LLVM's object files are safe by default because LLVM doesn't know how to produce SEH handlers. Reviewers: Bigcheese CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1691 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190898 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused code, which had been commented out.Preston Gurd2013-09-171-5/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190869 91177308-0d34-0410-b5e6-96231b3b80d8
* Add llvm.x86.* intrinsics for Intel SHA ExtensionsBen Langmuir2013-09-171-14/+26
| | | | | | | | | Add llvm.x86.* intrinsics for all of the Intel SHA Extensions instructions, as well as tests. Also remove mayLoad and hasSideEffects, which can be inferred from the instruction patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190864 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Converted to Unix styleElena Demikhovsky2013-09-171-3070/+3070
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190851 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AES and SHA instructions to the load folding tables.Craig Topper2013-09-171-0/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190850 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix column alignment. No functional change.Craig Topper2013-09-171-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190849 91177308-0d34-0410-b5e6-96231b3b80d8
* Make F16C feature flag imply AVX rather than just checking both at the patterns.Craig Topper2013-09-162-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190775 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the remaining Intel SHA instructionsBen Langmuir2013-09-141-0/+27
| | | | | | | | Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit xmm0 dependency. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190754 91177308-0d34-0410-b5e6-96231b3b80d8
* Adds support for Atom Silvermont (SLM) - -march=slmPreston Gurd2013-09-1313-196/+1000
| | | | | | | | | | | | | | Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
* Move operator to end of previous line to match coding standards.Craig Topper2013-09-131-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190659 91177308-0d34-0410-b5e6-96231b3b80d8
* Partial support for Intel SHA Extensions (sha1rnds4)Ben Langmuir2013-09-125-0/+29
| | | | | | | | | | Add basic assembly/disassembly support for the first Intel SHA instruction 'sha1rnds4'. Also includes feature flag, and test cases. Support for the remaining instructions will follow in a separate patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an instruction deprecation feature to TableGen.Joey Gouly2013-09-121-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | The 'Deprecated' class allows you to specify a SubtargetFeature that the instruction is deprecated on. The 'ComplexDeprecationPredicate' class allows you to define a custom predicate that is called to check for deprecation. For example: ComplexDeprecationPredicate<"MCR"> would mean you would have to define the following function: bool getMCRDeprecationInfo(MCInst &MI, MCSubtargetInfo &STI, std::string &Info) Which returns 'false' for not deprecated, and 'true' for deprecated and store the warning message in 'Info'. The MCTargetAsmParser constructor was chaned to take an extra argument of the MCInstrInfo class, so out-of-tree targets will need to be changed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190598 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: implemented extractelement with variable index.Elena Demikhovsky2013-09-126-3063/+3154
| | | | | | | Added parsing of mask register and "zeroing" semantic, like {%k1} {z}. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190595 91177308-0d34-0410-b5e6-96231b3b80d8
* Use the appropriate return type for the compact unwind encoding.Bill Wendling2013-09-111-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190551 91177308-0d34-0410-b5e6-96231b3b80d8
* Move into an anonymous namespace and closer to where it's used.Bill Wendling2013-09-111-26/+27
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190547 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r190366. It was breaking build bots.Bill Wendling2013-09-101-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190373 91177308-0d34-0410-b5e6-96231b3b80d8
* Use a default value for the prologue's debug location.Bill Wendling2013-09-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190366 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate compact unwind encoding from CFI directives.Bill Wendling2013-09-094-312/+359
| | | | | | | | | | | | | | | | We used to generate the compact unwind encoding from the machine instructions. However, this had the problem that if the user used `-save-temps' or compiled their hand-written `.s' file (with CFI directives), we wouldn't generate the compact unwind encoding. Move the algorithm that generates the compact unwind encoding into the MCAsmBackend. This way we can generate the encoding whether the code is from a `.ll' or `.s' file. <rdar://problem/13623355> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190290 91177308-0d34-0410-b5e6-96231b3b80d8
* Add neverHasSideEffects=1 on a couple move instructions.Craig Topper2013-09-082-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190259 91177308-0d34-0410-b5e6-96231b3b80d8
* Using popcount should check the popcount feature flag not the SSE41 feature ↵Craig Topper2013-09-081-2/+2
| | | | | | flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190258 91177308-0d34-0410-b5e6-96231b3b80d8
* [X86] Perform VSELECT DAG combines also before DAG type legalization.Juergen Ributzka2013-09-051-10/+11
| | | | | | | | | | | | | If the DAG already has only legal types, then the second round of DAG combines is skipped. In this case VSELECT+SETCC patterns that match a more efficient instruction (e.g. min/max) are never recognized. This fix allows VSELECT+SETCC combines if the types are already legal before DAG type legalization. Reviewer: Nadav git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190105 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a crash in the integrated assembler for Mach-O when a symbol differenceKevin Enderby2013-09-051-0/+4
| | | | | | | | | | | | | | expression uses an assembler temporary symbol from an assignment.  In this case the symbol does not have a fragment so the use of getFragment() would be NULL and caused a crash. In the case of an assembler temporary symbol we want to use the AliasedSymbol (if any) which will create a local relocation entry, but if it is not an assembler temporary symbol then let it use that symbol with an external relocation entry. rdar://9356266 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190096 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Mark non-crashing report_fatal_errors() as such.Jim Grosbach2013-09-031-13/+19
| | | | | | | | | Previously, the clang crash handling code would kick in and give a crash report for these, even though they're not that sort of error. rdar://14882264 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189878 91177308-0d34-0410-b5e6-96231b3b80d8
* WIP: Refactor some code so that it can be called by more than just one ↵Bill Wendling2013-09-031-60/+71
| | | | | | method. No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189849 91177308-0d34-0410-b5e6-96231b3b80d8
* Add hadSideEffects=0 to some instructions.Craig Topper2013-09-031-1/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189779 91177308-0d34-0410-b5e6-96231b3b80d8
* Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). ↵Craig Topper2013-09-023-0/+29
| | | | | | Fixes PR17028. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189742 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: updated the list of high-latency instructions.Elena Demikhovsky2013-09-021-1/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189740 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: gather-scatter tests; added foldable instructions;Elena Demikhovsky2013-09-021-1/+45
| | | | | | | Specify GATHER/SCATTER as heavy instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189736 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added GATHER and SCATTER instructions.Elena Demikhovsky2013-09-012-3/+285
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189729 91177308-0d34-0410-b5e6-96231b3b80d8
* Move everything depending on Object/MachOFormat.h over to Support/MachO.h.Charles Davis2013-09-013-84/+83
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189728 91177308-0d34-0410-b5e6-96231b3b80d8
* Build fixRichard Mitton2013-08-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189699 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixed a bug where diassembling an instruction that had a prefix would cause ↵Richard Mitton2013-08-301-7/+9
| | | | | | LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189698 91177308-0d34-0410-b5e6-96231b3b80d8
* Checking commit access; removed one space added in previous test checkin by JimAndrey Churbanov2013-08-301-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189673 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Add a description of the Intel Atom Silvermont CPU.Benjamin Kramer2013-08-301-0/+9
| | | | | | Currently this is just the atom model with SSE4.2 enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189669 91177308-0d34-0410-b5e6-96231b3b80d8
* Fixup BZHI selection to remove an unneeded zero extension.Craig Topper2013-08-302-13/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189656 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused X86andn_flag node.Craig Topper2013-08-301-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189654 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, ↵Craig Topper2013-08-303-21/+64
| | | | | | Y), -1)). Fixes PR17038. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189653 91177308-0d34-0410-b5e6-96231b3b80d8
* Clean up some usage of Triple. The base class has methods for determining ↵Cameron Esfahani2013-08-291-4/+2
| | | | | | if the target is iOS and Linux. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189604 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added extend and truncate instructions.Elena Demikhovsky2013-08-294-29/+245
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189580 91177308-0d34-0410-b5e6-96231b3b80d8
* The darwin integrated assembler for X86 in 64-bit mode is not rejectingKevin Enderby2013-08-291-1/+6
| | | | | | | | | | | | | 32-bit absolute addressing in instructions likei this: mov $_f, %rsi which is not supported in 64-bit mode. rdar://8827134 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189543 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added SQRT, VRSQRT14, VCOMISS, VUCOMISS, VRCP14, VPABSElena Demikhovsky2013-08-282-23/+466
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189472 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove support for the .debug_inlined section. No known softwareEric Christopher2013-08-281-1/+0
| | | | | | in use supports it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189439 91177308-0d34-0410-b5e6-96231b3b80d8
* X86JITInfo.cpp: Apply x64 version of X86CompilationCallback() to Cygwin64.NAKAMURA Takumi2013-08-281-1/+1
| | | | | | For now, (defined(X86_64_JIT) && defined(__CYGWIN__)) satisfies Cygwin64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189437 91177308-0d34-0410-b5e6-96231b3b80d8
* X86Subtarget.h: Recognize x86_64-cygwin.NAKAMURA Takumi2013-08-281-4/+1
| | | | | | In the LLVM side, x86_64-cygwin is almost as same as x86_64-mingw32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189436 91177308-0d34-0410-b5e6-96231b3b80d8
* [ms-inline asm] Support offsets after segment registersDavid Majnemer2013-08-271-40/+70
| | | | | | | | | | | | | | Summary: MASM let's you do stuff like 'MOV FS:20, EAX' and 'MOV EAX, FS:20' Reviewers: craig.topper, rnk Reviewed By: rnk CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1470 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189407 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added conversion instructions.Elena Demikhovsky2013-08-272-19/+214
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189349 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: Added FMA instructions.Elena Demikhovsky2013-08-272-1/+198
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189326 91177308-0d34-0410-b5e6-96231b3b80d8
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