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* Fix PR10422 by adding the necessary AVX UCOMISD memory versions toBruno Cardoso Lopes2011-07-221-2/+8
| | | | | | load folding logic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135801 91177308-0d34-0410-b5e6-96231b3b80d8
* Add v8f32->v8i32 bitcast. Fixes PR10440Bruno Cardoso Lopes2011-07-221-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135794 91177308-0d34-0410-b5e6-96231b3b80d8
* Turn shuffles into unpacks for VT == MVT::v2i64 and MVT::v2f64Rafael Espindola2011-07-221-9/+5
| | | | | | too. Patch by Jeff Muizelaar. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135789 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix x86's XALUO lowering to return its replacement values insteadDan Gohman2011-07-221-4/+2
| | | | | | | | of doing the RAUW calls for the overflow value itself. This makes it more consistent with how the rest of LegalizeDAG works. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135788 91177308-0d34-0410-b5e6-96231b3b80d8
* GCC complains about the angle of this line.Benjamin Kramer2011-07-221-1/+1
| | | | | | Remove the escaped newline. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135739 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the 128-bit special handling from SCALAR_TO_VECTOR. This isn'tBruno Cardoso Lopes2011-07-221-18/+0
| | | | | | | | the way to go. Doing this here will prevent several node matches later, and would have to force looking all the way through several VINSERTF128/VEXTRACTF128 chains to optimize simple things. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135730 91177308-0d34-0410-b5e6-96231b3b80d8
* -Inspected a AVX code block added by someone in early Feb. This was never usedBruno Cardoso Lopes2011-07-222-76/+25
| | | | | | | | | | | | | | | | and was actually very wrong, fix it and make it simpler. Also remove the ConcatVectors function, which is unused now. - Fix a introduction of useless nodes in r126664 and r126264. The VUNPCKL* should never be introduced cause we don't want duplicate nodes for 128 AVX and non-AVX modes, the actual instruction difference only exists during isel, but not for target specific DAG nodes. We only introduce V* target nodes when there is no 128-bit version already there. - Fix a fragile test and make it more useful. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135729 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a DAGCombine for transforming 128->256 casts into a simpleBruno Cardoso Lopes2011-07-221-7/+61
| | | | | | vxorps + vinsertf128 pair of instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135727 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce a new function to lower 256-bit vectors which are notBruno Cardoso Lopes2011-07-221-0/+14
| | | | | | | direclty supported and should be promoted and handled by smaller shuffles git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135726 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename function to be more specific and be more strict about its usageBruno Cardoso Lopes2011-07-221-6/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135725 91177308-0d34-0410-b5e6-96231b3b80d8
* - Register v16i16 as valid VR256 register classBruno Cardoso Lopes2011-07-212-19/+22
| | | | | | | | - Add more bitcasts for v16i16 - Since 135661 and 135662 already added the splat logic, just add one more splat test for v16i16 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135663 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for 256-bit versions of VPERMIL instruction. This is a newBruno Cardoso Lopes2011-07-217-0/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instruction introduced in AVX, which can operate on 128 and 256-bit vectors. It considers a 256-bit vector as two independent 128-bit lanes. It can permute any 32 or 64 elements inside a lane, and restricts the second lane to have the same permutation of the first one. With the improved splat support introduced early today, adding codegen for this instruction enable more efficient 256-bit code: Instead of: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vextractf128 $1, %ymm0, %xmm1 shufps $1, %xmm1, %xmm1 movss %xmm1, 28(%rsp) movss %xmm1, 24(%rsp) movss %xmm1, 20(%rsp) movss %xmm1, 16(%rsp) vextractf128 $0, %ymm0, %xmm0 shufps $1, %xmm0, %xmm0 movss %xmm0, 12(%rsp) movss %xmm0, 8(%rsp) movss %xmm0, 4(%rsp) movss %xmm0, (%rsp) vmovaps (%rsp), %ymm0 We get: vextractf128 $0, %ymm0, %xmm0 punpcklbw %xmm0, %xmm0 punpckhbw %xmm0, %xmm0 vinsertf128 $0, %xmm0, %ymm0, %ymm1 vinsertf128 $1, %xmm0, %ymm1, %ymm0 vpermilps $85, %ymm0, %ymm0 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135662 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve splat promotion to handle AVX types: v32i8 and v16i16. AlsoBruno Cardoso Lopes2011-07-211-24/+87
| | | | | | | | | refactor the code and add a bunch of comments. The final shuffle emitted by handling 256-bit types is suitable for the VPERM shuffle instruction which is going to be introduced in a next commit (with a testcase which cover this commit) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135661 91177308-0d34-0410-b5e6-96231b3b80d8
* Add aditional patterns for vextractf128 instructionBruno Cardoso Lopes2011-07-211-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135660 91177308-0d34-0410-b5e6-96231b3b80d8
* Add aditional patterns for vinsertf128 instructionBruno Cardoso Lopes2011-07-211-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135659 91177308-0d34-0410-b5e6-96231b3b80d8
* Add v16i16 type to VR256 classBruno Cardoso Lopes2011-07-211-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135658 91177308-0d34-0410-b5e6-96231b3b80d8
* Move code around. No functionality changesBruno Cardoso Lopes2011-07-211-65/+78
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135657 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up codeBruno Cardoso Lopes2011-07-211-15/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135656 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark instructions which are part of the frame setup with the ↵Bill Wendling2011-07-211-9/+20
| | | | | | MachineInstr::FrameSetup flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135645 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused function.Bill Wendling2011-07-201-64/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135635 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the now defunct getCompactUnwindEncoding method from the frame ↵Bill Wendling2011-07-202-118/+0
| | | | | | lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135634 91177308-0d34-0410-b5e6-96231b3b80d8
* Goodbye TargetAsmInfo. This eliminate last bit of CodeGen and Target in llvm-mc.Evan Cheng2011-07-203-103/+2
| | | | | | | | There is still a bit more refactoring left to do in Targets. But we are now very close to fixing all the layering issues in MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135611 91177308-0d34-0410-b5e6-96231b3b80d8
* Extend the hack for _GLOBAL_OFFSET_TABLE_ slightly; PR10389.Eli Friedman2011-07-201-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135607 91177308-0d34-0410-b5e6-96231b3b80d8
* - Move CodeModel from a TargetMachine global option to MCCodeGenInfo.Evan Cheng2011-07-203-36/+23
| | | | | | | | | - Introduce JITDefault code model. This tells targets to set different default code model for JIT. This eliminates the ugly hack in TargetMachine where code model is changed after construction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135580 91177308-0d34-0410-b5e6-96231b3b80d8
* X86Subtarget.h: Assume "x86_64-cygwin", though it has not been released yet, ↵NAKAMURA Takumi2011-07-201-1/+2
| | | | | | to appease test/CodeGen/X86 on cygwin. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135564 91177308-0d34-0410-b5e6-96231b3b80d8
* Introduce MCCodeGenInfo, which keeps information that can affect codegenEvan Cheng2011-07-193-72/+67
| | | | | | | | (including compilation, assembly). Move relocation model Reloc::Model from TargetMachine to MCCodeGenInfo so it's accessible even without TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135468 91177308-0d34-0410-b5e6-96231b3b80d8
* Move getInitialFrameState from TargetFrameInfo to MCAsmInfo (suggestions forEvan Cheng2011-07-184-25/+24
| | | | | | | better location welcome). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135438 91177308-0d34-0410-b5e6-96231b3b80d8
* Sink getDwarfRegNum, getLLVMRegNum, getSEHRegNum from TargetRegisterInfo downEvan Cheng2011-07-187-182/+189
| | | | | | | | | | to MCRegisterInfo. Also initialize the mapping at construction time. This patch eliminate TargetRegisterInfo from TargetAsmInfo. It's another step towards fixing the layering violation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135424 91177308-0d34-0410-b5e6-96231b3b80d8
* Be more smart with VCVTSS2SD. Also place the patterns close to theBruno Cardoso Lopes2011-07-181-20/+10
| | | | | | definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135407 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 128-bit sqrt versionsBruno Cardoso Lopes2011-07-181-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135404 91177308-0d34-0410-b5e6-96231b3b80d8
* land David Blaikie's patch to de-constify Type, with a few tweaks.Chris Lattner2011-07-185-31/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135375 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX 128-bit patterns for sint_to_fpBruno Cardoso Lopes2011-07-161-0/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135332 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a couple of things:Bruno Cardoso Lopes2011-07-151-61/+52
| | | | | | | | | | | | | | | | | | | | | | | | 1) Make non-legal 256-bit loads to be promoted to v4i64. This lets us canonize the loads and handle things the same way we use to handle for 128-bit registers. Despite of what one of the removed comments explained, the load promotion would not mess with VPERM, it's only a matter of doing the appropriate bitcasts when this instructions comes to be introduced. Also make LOAD v8i32 legal. 2) Doing 1) exposed two bugs: - v4i64 was being promoted to itself for several opcodes (introduced in r124447 by David Greene) causing endless recursion and the stack to explode. - there was no support for allOnes BUILD_VECTORs and ANDNP would fail to match because it was generating early target constant pools during lowering. 3) The testcases are already checked-in, doing 1) exposed the bugs in the current testcases. 4) Tidy up code to be more clear and explicit about AVX. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135313 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a few patterns for 256-bit bitcasts. No testcases now, they areBruno Cardoso Lopes2011-07-151-0/+9
| | | | | | comming together with other tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135312 91177308-0d34-0410-b5e6-96231b3b80d8
* PR10370: Make sure we know how to relax push correctly on x86-64.Eli Friedman2011-07-151-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135303 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove an unnecessary header from this file. I don't think this headerChandler Carruth2011-07-151-1/+0
| | | | | | | | | | was really intended, and it may have been required prior to some of the recent refactors. Including it however causes LLVMX86Desc to need symbols from LLVMX86CodeGen, forming a dependency cycle. This was masked in almost all builds: Clang, and GCC w/ optimizations didn't actually emit the symbols! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135242 91177308-0d34-0410-b5e6-96231b3b80d8
* Move some parts of TargetAsmInfo down to MCAsmInfo. This is not the greatestEvan Cheng2011-07-152-17/+22
| | | | | | | | solution but it is a small step towards removing the horror that is TargetAsmInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135237 91177308-0d34-0410-b5e6-96231b3b80d8
* Major update to CMake build to reflect changes in r135219 in theChandler Carruth2011-07-152-2/+6
| | | | | | | | | | | | backend. Moved some MCAsmInfo files down into the MCTargetDesc sublibraries, removed some (i suspect long) dead files from other parts of the CMake build, etc. Also copied the include directory hack from the Makefile. Finally, updated the lib deps. I spot checked this, and think its correct, but review appreciated there. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135234 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename createAsmInfo to createMCAsmInfo and move registration code to ↵Evan Cheng2011-07-145-35/+37
| | | | | | MCTargetDesc to prepare for next round of changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135219 91177308-0d34-0410-b5e6-96231b3b80d8
* * Redo the permutation encoding for frameless stacks to be more like what theBill Wendling2011-07-141-44/+73
| | | | | | | | unwind library expects. * Comment the permutation encoding for frameless stacks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135202 91177308-0d34-0410-b5e6-96231b3b80d8
* Port operand types for ARM and X86 over from EDIS to the .td files.Benjamin Kramer2011-07-142-1/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135198 91177308-0d34-0410-b5e6-96231b3b80d8
* Next round of MC refactoring. This patch factor MC table instantiations, MCEvan Cheng2011-07-147-11/+3
| | | | | | | registeration and creation code into XXXMCDesc libraries. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
* Check register class matching instead of width of type matchingEric Christopher2011-07-141-4/+4
| | | | | | | | | when determining validity of matching constraint. Allow i1 types access to the GR8 reg class for x86. Fixes PR10352 and rdar://9777108 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135180 91177308-0d34-0410-b5e6-96231b3b80d8
* Add 256-bit load/store recognition and matching in several places.Bruno Cardoso Lopes2011-07-142-4/+74
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135171 91177308-0d34-0410-b5e6-96231b3b80d8
* [VECTOR-SELECT]Nadav Rotem2011-07-142-2/+65
| | | | | | | | | | | | | During type legalization we often use the SIGN_EXTEND_INREG SDNode. When this SDNode is legalized during the LegalizeVector phase, it is scalarized because non-simple types are automatically marked to be expanded. In this patch we add support for lowering SIGN_EXTEND_INREG manually. This fixes CodeGen/X86/vec_sext.ll when running with the '-promote-elements' flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135144 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix up assertion in r135018 so it doesn't trigger on 32-bit; when we're in ↵Eli Friedman2011-07-141-1/+2
| | | | | | 32-bit, it doesn't matter whether the operation overflows because the computed address is not wider than the immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135120 91177308-0d34-0410-b5e6-96231b3b80d8
* Add code to handle a "frameless" unwind stack.Bill Wendling2011-07-131-13/+55
| | | | | | | | The frameless unwind stack has a special encoding, the algorithm for which is in "permuteEncode". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135103 91177308-0d34-0410-b5e6-96231b3b80d8
* Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A moreBruno Cardoso Lopes2011-07-133-64/+37
| | | | | | | general version of X86ISD::ANDNP also opened the room for a little bit of refactoring. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135088 91177308-0d34-0410-b5e6-96231b3b80d8
* The target specific node PANDN name is misleading. That happens becauseBruno Cardoso Lopes2011-07-134-12/+12
| | | | | | | it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN instruction. Rename it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135087 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure we don't combine a large displacement and a frame index in the ↵Eli Friedman2011-07-131-8/+25
| | | | | | | | | | same addressing mode on x86-64. It can overflow, leading to a crash/miscompile. <rdar://problem/9763308> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135084 91177308-0d34-0410-b5e6-96231b3b80d8
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