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* Wrap at 80 colsChris Lattner2004-04-011-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12587 91177308-0d34-0410-b5e6-96231b3b80d8
* Generate slightly smaller code, "test R, R" instead of "cmp R, 0"Chris Lattner2004-03-312-10/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12579 91177308-0d34-0410-b5e6-96231b3b80d8
* The X86 backend no longer needs the select lowering pass.Chris Lattner2004-03-311-6/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12578 91177308-0d34-0410-b5e6-96231b3b80d8
* Codegen FP select instructions into X86 conditional moves. Annoyingly enoughChris Lattner2004-03-312-28/+72
| | | | | | | | the X86 does not support a full set of fp cmove instructions, so we can't always fold the condition into the select. :( Yuck. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12577 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for floating point conditional move instructionsChris Lattner2004-03-312-10/+74
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12576 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for FP cmovesChris Lattner2004-03-312-20/+56
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12575 91177308-0d34-0410-b5e6-96231b3b80d8
* Add FP conditional move instructions, which annoyingly have special propertiesChris Lattner2004-03-313-10/+33
| | | | | | | | that require the asmwriter to be extended (printing implicit uses before the explicit operands) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12574 91177308-0d34-0410-b5e6-96231b3b80d8
* Fold comparisons into select instructions, making much better code andChris Lattner2004-03-302-60/+172
| | | | | | | using our broad selection of movcc instructions. :) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12560 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement spill code folding for all of the conditional move instructionsChris Lattner2004-03-301-0/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12554 91177308-0d34-0410-b5e6-96231b3b80d8
* Add direct support for integer select instructions, though we still don't ↵Chris Lattner2004-03-303-4/+194
| | | | | | | | | support folding compares into the select yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12553 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some serious bugs in the cmov descriptions, which didn't cause a problem ↵Chris Lattner2004-03-301-60/+60
| | | | | | | | | | | because we never generated them Make indentation a bit more consistent git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12549 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a fairly major performance problem. If a PHI node had a constant asChris Lattner2004-03-302-22/+36
| | | | | | | | | | an incoming value from a block, the selector would evaluate the constant at the TOP of the block instead of at the end of the block. This made the live range for the constant span the entire block, increasing register pressure needlessly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12542 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the select lowering pass to get initial support for select instructionsChris Lattner2004-03-301-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12541 91177308-0d34-0410-b5e6-96231b3b80d8
* Malloc doesn't kill a load. This patch need not go into 1.2 though.Chris Lattner2004-03-182-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12500 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a really nasty bug that was breaking ijpeg in LLC mode. We were incorrectlyChris Lattner2004-03-182-0/+4
| | | | | | | | folding load instructions into other instructions across free instruction boundaries. Perhaps this will also fix the other strange failures? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12494 91177308-0d34-0410-b5e6-96231b3b80d8
* Add LAHF instructionAlkis Evlogimenos2004-03-151-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12424 91177308-0d34-0410-b5e6-96231b3b80d8
* Another API change to MRegisterInfo::foldMemoryOperand. Instead of aAlkis Evlogimenos2004-03-142-5/+4
| | | | | | | MachineBasicBlock::iterator take a MachineInstr*. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12392 91177308-0d34-0410-b5e6-96231b3b80d8
* Change MRegisterInfo::foldMemoryOperand to return the foldedAlkis Evlogimenos2004-03-142-171/+166
| | | | | | | instruction to make the API more flexible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12386 91177308-0d34-0410-b5e6-96231b3b80d8
* It helps if I save the file. :)Chris Lattner2004-03-132-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12357 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename the intrinsic enum values for llvm.va_* from Intrinsic::va_* toChris Lattner2004-03-132-6/+6
| | | | | | | Intrinsic::va*. This avoid conflicting with macros in the stdlib.h file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12356 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for a wider range of CMOV instructions.Alkis Evlogimenos2004-03-121-2/+54
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12336 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix compilation on Sparc: assert(0) => abort()Misha Brukman2004-03-112-10/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12289 91177308-0d34-0410-b5e6-96231b3b80d8
* Check if printing of implicit uses is required for all types of shiftAlkis Evlogimenos2004-03-092-0/+6
| | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12258 91177308-0d34-0410-b5e6-96231b3b80d8
* Differentiate between extended precision floats (80-bit) and double ↵Alkis Evlogimenos2004-03-091-1/+1
| | | | | | precision floats (64-bit) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12254 91177308-0d34-0410-b5e6-96231b3b80d8
* Use newly added API to emit bytes for instructions that gas misassemblesAlkis Evlogimenos2004-03-092-132/+106
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12253 91177308-0d34-0410-b5e6-96231b3b80d8
* Add emitInstruction() API so that we can get the bytes of a simple instructionAlkis Evlogimenos2004-03-092-3/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12252 91177308-0d34-0410-b5e6-96231b3b80d8
* Constify things a bitAlkis Evlogimenos2004-03-091-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12251 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement folding explicit load instructions into binary operations. For aChris Lattner2004-03-082-0/+162
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | testcase like this: int %test(int* %P, int %A) { %Pv = load int* %P %B = add int %A, %Pv ret int %B } We now generate: test: mov %ECX, DWORD PTR [%ESP + 4] mov %EAX, DWORD PTR [%ESP + 8] add %EAX, DWORD PTR [%ECX] ret Instead of: test: mov %EAX, DWORD PTR [%ESP + 4] mov %ECX, DWORD PTR [%ESP + 8] mov %EAX, DWORD PTR [%EAX] add %EAX, %ECX ret ... saving one instruction, and often a register. Note that there are a lot of other instructions that could use this, but they aren't handled. I'm not really interested in adding them, but mul/div and all of the FP instructions could be supported as well if someone wanted to add them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12204 91177308-0d34-0410-b5e6-96231b3b80d8
* Rearrange and refactor some code. No functionality changes.Chris Lattner2004-03-082-202/+192
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12203 91177308-0d34-0410-b5e6-96231b3b80d8
* Add memory operand version of conditional move.Alkis Evlogimenos2004-03-072-3/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12190 91177308-0d34-0410-b5e6-96231b3b80d8
* make -print-machineinstrs work for both SparcV9 and X86Brian Gaeke2004-03-041-10/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12122 91177308-0d34-0410-b5e6-96231b3b80d8
* Add assertion for scale verification.Alkis Evlogimenos2004-03-041-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12120 91177308-0d34-0410-b5e6-96231b3b80d8
* Doxygenify some comments.Misha Brukman2004-03-014-18/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12064 91177308-0d34-0410-b5e6-96231b3b80d8
* TargetCacheInfo has been removed; its only uses were to propagate a constantBrian Gaeke2004-03-011-9/+5
| | | | | | | | | | (16) into certain areas of the SPARC V9 back-end. I'm fairly sure the US IIIi's dcache has 32-byte lines, so I'm not sure where the 16 came from. However, in the interest of not breaking things any more than they already are, I'm going to leave the constant alone. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12043 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle passing constant integers to functions much more efficiently. InsteadChris Lattner2004-03-012-20/+46
| | | | | | | | | | | | | | | | | | | | | | | | of generating this code: mov %EAX, 4 mov DWORD PTR [%ESP], %EAX mov %AX, 123 movsx %EAX, %AX mov DWORD PTR [%ESP + 4], %EAX call Y we now generate: mov DWORD PTR [%ESP], 4 mov DWORD PTR [%ESP + 4], 123 call Y Which hurts the eyes less. :) Considering that register pressure around call sites is already high (with all of the callee clobber registers n stuff), this may help a lot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12028 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a minor code-quality issue. When passing 8 and 16-bit integer constantsChris Lattner2004-03-012-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to function calls, we would emit dead code, like this: int Y(int, short, double); int X() { Y(4, 123, 4); } --- Old X: sub %ESP, 20 mov %EAX, 4 mov DWORD PTR [%ESP], %EAX *** mov %AX, 123 mov %AX, 123 movsx %EAX, %AX mov DWORD PTR [%ESP + 4], %EAX fld QWORD PTR [.CPIX_0] fstp QWORD PTR [%ESP + 8] call Y mov %EAX, 0 # IMPLICIT_USE %EAX %ESP add %ESP, 20 ret Now we emit: X: sub %ESP, 20 mov %EAX, 4 mov DWORD PTR [%ESP], %EAX mov %AX, 123 movsx %EAX, %AX mov DWORD PTR [%ESP + 4], %EAX fld QWORD PTR [.CPIX_0] fstp QWORD PTR [%ESP + 8] call Y mov %EAX, 0 # IMPLICIT_USE %EAX %ESP add %ESP, 20 ret Next up, eliminate the mov AX and movsx entirely! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12026 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction name description.Alkis Evlogimenos2004-02-291-2/+19
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11998 91177308-0d34-0410-b5e6-96231b3b80d8
* Use correct template for SHLD and SHRD instructions so that the memoryAlkis Evlogimenos2004-02-291-9/+9
| | | | | | | operand size is correctly specified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11997 91177308-0d34-0410-b5e6-96231b3b80d8
* Improve allocation order:Alkis Evlogimenos2004-02-291-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1) For 8-bit registers try to use first the ones that are parts of the same register (AL then AH). This way we only alias 2 16/32-bit registers after allocating 4 8-bit variables. 2) Move EBX as the last register to allocate. This will cause less spills to happen since we will have 8-bit registers available up to register excaustion (assuming we use the allocation order). It would be nice if we could push all of the 8-bit aliased registers towards the end but we much prefer to keep callee saved register to the end to avoid saving them on entry and exit of the function. For example this gives a slight reduction of spills with linear scan on 164.gzip. Before: 11221 asm-printer - Number of machine instrs printed 975 spiller - Number of loads added 675 spiller - Number of stores added 398 spiller - Number of register spills After: 11182 asm-printer - Number of machine instrs printed 952 spiller - Number of loads added 652 spiller - Number of stores added 386 spiller - Number of register spills git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11996 91177308-0d34-0410-b5e6-96231b3b80d8
* A big X86 instruction rename. The instructions are renamed to makeAlkis Evlogimenos2004-02-2911-1021/+1021
| | | | | | | | | | | | | | | | | their names more decriptive. A name consists of the base name, a default operand size followed by a character per operand with an optional special size. For example: ADD8rr -> add, 8-bit register, 8-bit register IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11995 91177308-0d34-0410-b5e6-96231b3b80d8
* Eliminate the X86-specific BMI functions, using BuildMI instead.Chris Lattner2004-02-292-374/+352
| | | | | | | Replace uses of addZImm with addImm. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11992 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a miscompilation of 197.parser that occurs when you have single basicChris Lattner2004-02-292-16/+28
| | | | | | | block loops. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11990 91177308-0d34-0410-b5e6-96231b3b80d8
* Adjust to change in TII ctor argumentsChris Lattner2004-02-291-3/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11987 91177308-0d34-0410-b5e6-96231b3b80d8
* These two virtual methods are never called.Chris Lattner2004-02-294-41/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11984 91177308-0d34-0410-b5e6-96231b3b80d8
* Use correct template for ADC instruction with memory operands.Alkis Evlogimenos2004-02-291-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11974 91177308-0d34-0410-b5e6-96231b3b80d8
* SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename themAlkis Evlogimenos2004-02-284-14/+14
| | | | | | | to denote this fact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11972 91177308-0d34-0410-b5e6-96231b3b80d8
* Floating point loads/stores act on memory operands. Rename them toAlkis Evlogimenos2004-02-288-71/+71
| | | | | | | denote this fact. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11971 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename instruction templates to be easier to the human eye toAlkis Evlogimenos2004-02-281-254/+254
| | | | | | | | | | | | parse. The name is now I (operand size)*. For example: Im32 -> instruction with 32-bit memory operands. Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11970 91177308-0d34-0410-b5e6-96231b3b80d8
* Uncomment instructions that take both an immediate and a memoryAlkis Evlogimenos2004-02-283-21/+11
| | | | | | | operand but their sizes differ. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11969 91177308-0d34-0410-b5e6-96231b3b80d8
* Each instruction now has both an ImmType and a MemType. This describesAlkis Evlogimenos2004-02-286-500/+542
| | | | | | | | | the size of the immediate and the memory operand on instructions that use them. This resolves problems with instructions that take both a memory and an immediate operand but their sizes differ (i.e. ADDmi32b). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11967 91177308-0d34-0410-b5e6-96231b3b80d8
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