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* Add AVX movnt{pd,ps,dq} 256-bit intrinsicsBruno Cardoso Lopes2010-08-101-0/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110650 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX movmsk 256-bit intrinsicsBruno Cardoso Lopes2010-08-101-8/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110648 91177308-0d34-0410-b5e6-96231b3b80d8
* Support AVX 256-bit load and store intrinsicsBruno Cardoso Lopes2010-08-102-6/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110645 91177308-0d34-0410-b5e6-96231b3b80d8
* Patterns to match AVX cmp instructionsBruno Cardoso Lopes2010-08-101-10/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110633 91177308-0d34-0410-b5e6-96231b3b80d8
* Add matching patterns for vblend AVX intrinsicsBruno Cardoso Lopes2010-08-101-11/+6
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* Wording.Eric Christopher2010-08-091-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110618 91177308-0d34-0410-b5e6-96231b3b80d8
* Add VCVTPD2PS, VCVTPS2DQ, VCVTPS2PDY, VCVTTPD2DQY, VCVTTPS2DQ and VCVTPD2DQ ↵Bruno Cardoso Lopes2010-08-091-0/+30
| | | | | | 256-bit conversion intrinsics git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110608 91177308-0d34-0410-b5e6-96231b3b80d8
* Add patterns to AVX conversions instructions. Do that instead of declaring ↵Bruno Cardoso Lopes2010-08-091-9/+20
| | | | | | more intructions whenever is possible, more coming git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110605 91177308-0d34-0410-b5e6-96231b3b80d8
* CMake: eliminated unnecessary target_link_libraries.Oscar Fuentes2010-08-091-1/+0
| | | | | | | | Next time the build is broken due to wrong library dependencies, just try building again (if you are on some Unix and are building all LLVM targets) or ask someone to commit the regenerated LLVMLibDeps.cmake. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110593 91177308-0d34-0410-b5e6-96231b3b80d8
* Memory version of vcvtdq2pd intrinsicBruno Cardoso Lopes2010-08-091-1/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110582 91177308-0d34-0410-b5e6-96231b3b80d8
* Patterns to match vinsert, vbroadcast, vmovmask and vcvtdq2pd AVX intrinsicsBruno Cardoso Lopes2010-08-091-20/+59
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110580 91177308-0d34-0410-b5e6-96231b3b80d8
* Use sdmem and sse_load_f64 (etc.) for the vectorDale Johannesen2010-08-071-8/+13
| | | | | | | | | | form of CMPSD (etc.) Matching a 128-bit memory operand is wrong, the instruction uses only 64 bits (same as ADDSD etc.) 8193553. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110491 91177308-0d34-0410-b5e6-96231b3b80d8
* Patterns to match AVX 256-bit vzero intrinsicsBruno Cardoso Lopes2010-08-061-4/+4
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* Patterns to match AVX 256-bit permutation intrinsicsBruno Cardoso Lopes2010-08-062-13/+48
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110468 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r110396, with fixes to appease the Linux buildbot gods.Owen Anderson2010-08-065-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110460 91177308-0d34-0410-b5e6-96231b3b80d8
* Patterns to match AVX 256-bit horizontal arithmetic intrinsicsBruno Cardoso Lopes2010-08-061-14/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110427 91177308-0d34-0410-b5e6-96231b3b80d8
* Patterns to match AVX 256-bit arithmetic intrinsicsBruno Cardoso Lopes2010-08-061-30/+75
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110425 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r110396 to fix buildbots.Owen Anderson2010-08-065-6/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110410 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an option to always emit realignment code for a particular module.Eric Christopher2010-08-051-1/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110404 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't use PassInfo* as a type identifier for passes. Instead, use the ↵Owen Anderson2010-08-055-6/+6
| | | | | | | | | address of the static ID member as the sole unique type identifier. Clean up APIs related to this change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110396 91177308-0d34-0410-b5e6-96231b3b80d8
* Support very basic (doesn't include ABI support in the front-end, varags, ↵Bruno Cardoso Lopes2010-08-052-4/+30
| | | | | | ...) 256-bit argument passing and return for AVX git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110394 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle the memory barrier pseudo that goes to nothing for the JIT.Eric Christopher2010-08-051-1/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110371 91177308-0d34-0410-b5e6-96231b3b80d8
* Set hasSideEffects on the 64-bit no-sse memory barrier.Eric Christopher2010-08-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110369 91177308-0d34-0410-b5e6-96231b3b80d8
* Be a little bit more specific about target for the memory barrierEric Christopher2010-08-052-2/+4
| | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110360 91177308-0d34-0410-b5e6-96231b3b80d8
* Handle the pseudo in MCInstLower.Eric Christopher2010-08-051-0/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110359 91177308-0d34-0410-b5e6-96231b3b80d8
* Make x86-64 membarriers work without sse and clean up some of theEric Christopher2010-08-043-4/+14
| | | | | | | uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110274 91177308-0d34-0410-b5e6-96231b3b80d8
* PR7814: Truncates cannot be ignored for signed comparisons.Eli Friedman2010-08-041-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110268 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DEBUG message.Devang Patel2010-08-041-0/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110224 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable COFF writer on mingw32 and cygwin.Benjamin Kramer2010-08-041-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110200 91177308-0d34-0410-b5e6-96231b3b80d8
* Print an error message when someone tries -integrated-as on an unsupported ↵Benjamin Kramer2010-08-041-1/+7
| | | | | | | | | | | target. - The COFF backend doesn't support MingW/Cygwin at the moment, it'll report an error, but it's still much better than random assertions from the MachO backend. - We want to make ELF the default eventually, it's what the majority of targets use. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110197 91177308-0d34-0410-b5e6-96231b3b80d8
* fix a win64 encoding problem, patch by Cameron Esfahani!Chris Lattner2010-08-031-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110164 91177308-0d34-0410-b5e6-96231b3b80d8
* MC: Remove HasAbsolutizedSet from WindowsX86AsmBackend.Michael J. Spencer2010-07-311-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109949 91177308-0d34-0410-b5e6-96231b3b80d8
* Add relax all support to the COFF object streamer.Michael J. Spencer2010-07-311-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109947 91177308-0d34-0410-b5e6-96231b3b80d8
* Support all 128-bit AVX vector intrinsics. Most part of them I alreadyBruno Cardoso Lopes2010-07-303-232/+240
| | | | | | | | | | | | | declared during the addition of the assembler support, the additional changes are: - Add missing intrinsics - Move all SSE conversion instructions in X86InstInfo64.td to the SSE.td file. - Duplicate some patterns to AVX mode. - Step into PCMPEST/PCMPIST custom inserter and add AVX versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109878 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix typo!Bruno Cardoso Lopes2010-07-301-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109877 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r109652, and remove the offending assert in loadRegFromStackSlot instead.Jakob Stoklund Olesen2010-07-292-6/+1
| | | | | | | | | | | | We do sometimes load from a too small stack slot when dealing with x86 arguments (varargs and smaller-than-32-bit args). It looks like we know what we are doing in those cases, so I am going to remove the assert instead of artifically enlarging stack slot sizes. The assert in storeRegToStackSlot stays in. We don't want to write beyond the bounds of a stack slot. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109764 91177308-0d34-0410-b5e6-96231b3b80d8
* Create a fixed stack object for varargs that is as large as any register.Jakob Stoklund Olesen2010-07-281-1/+4
| | | | | | | | | | The size of this object isn't used for anything - technically it is of variable size. This avoids a false positive from the assert in X86InstrInfo::loadRegFromStackSlot, and fixes PR7735. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109652 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement a vectorized algorithm for <16 x i8> << <16 x i8>Nate Begeman2010-07-281-21/+73
| | | | | | | This is about 4x faster and smaller than the existing scalarization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109566 91177308-0d34-0410-b5e6-96231b3b80d8
* ~40% faster vector shl <4 x i32> on SSE 4.1 Larger improvements for smaller ↵Nate Begeman2010-07-272-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | types coming in future patches. For: define <2 x i64> @shl(<4 x i32> %r, <4 x i32> %a) nounwind readnone ssp { entry: %shl = shl <4 x i32> %r, %a ; <<4 x i32>> [#uses=1] %tmp2 = bitcast <4 x i32> %shl to <2 x i64> ; <<2 x i64>> [#uses=1] ret <2 x i64> %tmp2 } We get: _shl: ## @shl pslld $23, %xmm1 paddd LCPI0_0, %xmm1 cvttps2dq %xmm1, %xmm1 pmulld %xmm1, %xmm0 ret Instead of: _shl: ## @shl pshufd $3, %xmm0, %xmm2 movd %xmm2, %eax pshufd $3, %xmm1, %xmm2 movd %xmm2, %ecx shll %cl, %eax movd %eax, %xmm2 pshufd $1, %xmm0, %xmm3 movd %xmm3, %eax pshufd $1, %xmm1, %xmm3 movd %xmm3, %ecx shll %cl, %eax movd %eax, %xmm3 punpckldq %xmm2, %xmm3 movd %xmm0, %eax movd %xmm1, %ecx shll %cl, %eax movd %eax, %xmm2 movhlps %xmm0, %xmm0 movd %xmm0, %eax movhlps %xmm1, %xmm1 movd %xmm1, %ecx shll %cl, %eax movd %eax, %xmm0 punpckldq %xmm0, %xmm2 movdqa %xmm2, %xmm0 punpckldq %xmm3, %xmm0 ret git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109549 91177308-0d34-0410-b5e6-96231b3b80d8
* Make MC use Windows COFF on Windows and add tests.Michael J. Spencer2010-07-272-0/+23
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109494 91177308-0d34-0410-b5e6-96231b3b80d8
* The isLoadFromStackSlot and isStoreToStackSlot have no way of reportingJakob Stoklund Olesen2010-07-271-2/+3
| | | | | | | | | | | | | subregister operands like this: %reg1040:sub_32bit<def> = MOV32rm <fi#-2>, 1, %reg0, 0, %reg0, %reg1040<imp-def>; mem:LD4[FixedStack-2](align=8) Make them return false when subreg operands are present. VirtRegRewriter is making bad assumptions otherwise. This fixes PR7713. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109489 91177308-0d34-0410-b5e6-96231b3b80d8
* Add assertions that expose the PR7713 miscompilation: Accessing a stack slotJakob Stoklund Olesen2010-07-271-0/+4
| | | | | | with a too-big register class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109488 91177308-0d34-0410-b5e6-96231b3b80d8
* On x86, f32 / f64 nodes share the same registers as 128-bit vector values.Evan Cheng2010-07-262-0/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109450 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporary hack to let codegen assert or generate poor code in caseBruno Cardoso Lopes2010-07-261-8/+13
| | | | | | | | | | | we are using AVX and no AVX version of the desired intruction is present, this is better for incremental dev (without fallbacks it's easier to spot what's missing). Not sure this is the best hack thought (we can also disable all HasSSE* predicates by dinamically marking them 'false' if AVX is present) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109434 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an ILP scheduler. This is a register pressure aware scheduler that'sEvan Cheng2010-07-242-0/+21
| | | | | | | | | | | | | appropriate for targets without detailed instruction iterineries. The scheduler schedules for increased instruction level parallelism in low register pressure situation; it schedules to reduce register pressure when the register pressure becomes high. On x86_64, this is a win for all tests in CFP2000. It also sped up 256.bzip2 by 16%. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109300 91177308-0d34-0410-b5e6-96231b3b80d8
* Support x86 "eiz" and "riz" pseudo index registers in the assembler.Bruno Cardoso Lopes2010-07-243-1/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109295 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove trailing whitespaceBruno Cardoso Lopes2010-07-231-30/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109276 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX version of CLMUL instructionsBruno Cardoso Lopes2010-07-233-0/+58
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* Declare CLMUL as a subtarget featureBruno Cardoso Lopes2010-07-231-0/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109207 91177308-0d34-0410-b5e6-96231b3b80d8
* Add x86 CLMUL (Carry-less multiplication) cpu featureBruno Cardoso Lopes2010-07-233-3/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109206 91177308-0d34-0410-b5e6-96231b3b80d8
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