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* AVX: Add support for vbroadcast from BUILD_VECTOR and refactor some of the ↵Nadav Rotem2011-11-151-48/+85
| | | | | | | | | vbroadcast code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144720 91177308-0d34-0410-b5e6-96231b3b80d8
* Added custom lowering for load->dec->store sequence in x86 when the EFLAGS ↵Pete Cooper2011-11-152-2/+61
| | | | | | | | | | | | | registers is used by later instructions. Only done for DEC64m right now. Fixes <rdar://problem/6172640> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144705 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some unnecessary includes of PseudoSourceValue.h.Jay Foad2011-11-153-3/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144631 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix PR11370 for real. Prevents converting 256-bit FP instruction to AVX2 ↵Craig Topper2011-11-151-9/+17
| | | | | | 256-bit integer instructions when AVX2 isn't enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144629 91177308-0d34-0410-b5e6-96231b3b80d8
* Properly qualify AVX2 specific parts of execution dependency table. Also ↵Craig Topper2011-11-152-9/+16
| | | | | | enable converting between 256-bit PS/PD operations when AVX1 is enabled. Fixes PR11370. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144622 91177308-0d34-0410-b5e6-96231b3b80d8
* Break false dependencies before partial register updates.Jakob Stoklund Olesen2011-11-152-0/+57
| | | | | | | | | | | | | | Two new TargetInstrInfo hooks lets the target tell ExecutionDepsFix about instructions with partial register updates causing false unwanted dependencies. The ExecutionDepsFix pass will break the false dependencies if the updated register was written in the previoius N instructions. The small loop added to sse-domains.ll runs twice as fast with dependency-breaking instructions inserted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144602 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a missing pattern for X86ISD::MOVLPD. rdar://10436044Evan Cheng2011-11-141-0/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144566 91177308-0d34-0410-b5e6-96231b3b80d8
* Changed SSE4/AVX <2 x i64> extract and insert ops to be Custom loweredPete Cooper2011-11-141-5/+8
| | | | | | | | | Constant idx case is still done in tablegen but other cases are then expanded Fixes <rdar://problem/10435460> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144557 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX2 version of instructions to load folding tables. Also add a bunch of ↵Craig Topper2011-11-141-2/+139
| | | | | | missing SSE/AVX instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144525 91177308-0d34-0410-b5e6-96231b3b80d8
* Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX ↵Craig Topper2011-11-142-19/+37
| | | | | | instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144522 91177308-0d34-0410-b5e6-96231b3b80d8
* Add BLSI, BLSMSK, and BLSR to getTargetNodeName.Craig Topper2011-11-131-2/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144502 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more AVX2 shift lowering support. Move AVX2 variable shift to use ↵Craig Topper2011-11-122-62/+153
| | | | | | patterns instead of custom lowering code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144457 91177308-0d34-0410-b5e6-96231b3b80d8
* build: Attempt to rectify inconsistencies between CMake and LLVMBuild ↵Daniel Dunbar2011-11-123-2/+3
| | | | | | | | versions of explicit dependencies. - The hope is that we have a tool/test to verify these are accurate (and tight) soon. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144444 91177308-0d34-0410-b5e6-96231b3b80d8
* Add lowering for AVX2 shift instructions.Craig Topper2011-11-112-117/+167
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144380 91177308-0d34-0410-b5e6-96231b3b80d8
* If we have to reset the calculation of the compact encoding, then also reset theBill Wendling2011-11-111-0/+1
| | | | | | | | "saved register" index. <rdar://problem/10430076> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144350 91177308-0d34-0410-b5e6-96231b3b80d8
* LLVMBuild: Add explicit information on whether targets define an assembly ↵Daniel Dunbar2011-11-111-0/+3
| | | | | | printer, assembly parser, or disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144344 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX2: Add variable shift from memory.Nadav Rotem2011-11-101-1/+24
| | | | | | | | | Note: These patterns only works in some cases because many times the load sd node is bitcasted from a load node of a different type. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144266 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-build: Add --native-target and --enable-targets options, and add logic toDaniel Dunbar2011-11-101-1/+0
| | | | | | | | | | handle defining the "magic" target related components (like native, nativecodegen, and engine). - We still require these components to be in the project (currently in lib/Target) so that we have a place to document them and hopefully make it more obvious that they are "magic". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144253 91177308-0d34-0410-b5e6-96231b3b80d8
* llvm-build: Add an explicit component type to represent targets.Daniel Dunbar2011-11-101-1/+2
| | | | | | - Gives us a place to hang target specific metadata (like whether the target has a JIT). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144250 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX2: Add patterns for variable shift operationsNadav Rotem2011-11-092-0/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144212 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary include.Devang Patel2011-11-091-1/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144211 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX2 support for vselect of v32i8Nadav Rotem2011-11-092-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144187 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable execution dependency fix pass for YMM registers when AVX2 is enabled. ↵Craig Topper2011-11-092-4/+20
| | | | | | Add AVX2 logical operations to list of replaceable instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144179 91177308-0d34-0410-b5e6-96231b3b80d8
* Add instruction selection for AVX2 integer comparisons.Craig Topper2011-11-092-8/+43
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144176 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX2 instruction lowering for add, sub, and mul.Craig Topper2011-11-091-24/+81
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144174 91177308-0d34-0410-b5e6-96231b3b80d8
* Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2011-11-081-33/+41
| | | | | | | When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144100 91177308-0d34-0410-b5e6-96231b3b80d8
* Add x86 isel logic and patterns to match movlps from clang generated IR for ↵Evan Cheng2011-11-082-6/+11
| | | | | | _mm_loadl_pi(). rdar://10134392, rdar://10050222 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144052 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand V_SET0 to xorps by default.Jakob Stoklund Olesen2011-11-071-1/+1
| | | | | | | | | The xorps instruction is smaller than pxor, so prefer that encoding. The ExecutionDepsFix pass will switch the encoding to pxor and xorpd when appropriate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143996 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX2 variable shift instructions and intrinsics.Craig Topper2011-11-071-0/+40
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143915 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX2 VPMOVMASK instructions and intrinsics.Craig Topper2011-11-071-0/+38
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143904 91177308-0d34-0410-b5e6-96231b3b80d8
* Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be ↵Craig Topper2011-11-071-2/+38
| | | | | | qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143902 91177308-0d34-0410-b5e6-96231b3b80d8
* More AVX2 instructions and their intrinsics.Craig Topper2011-11-064-14/+80
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143895 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace (Lower|Upper)caseString in favor of StringRef's newest methods.Benjamin Kramer2011-11-062-8/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143891 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more AVX2 instructions and intrinsics.Craig Topper2011-11-062-13/+96
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143861 91177308-0d34-0410-b5e6-96231b3b80d8
* Add more PRI.64 macros for MSVC and use them throughout the codebase.Benjamin Kramer2011-11-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143799 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhanced vzeroupper insertion pass that avoids inserting vzeroupper where it ↵Eli Friedman2011-11-041-27/+207
| | | | | | | | | | is unnecessary through local analysis. Patch from Bruno Cardoso Lopes, with some additional changes. I'm going to wait for any review comments and perform some additional testing before turning this on by default. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143750 91177308-0d34-0410-b5e6-96231b3b80d8
* build/cmake: Use tblgen macro directly instead of llvm_tablegen, which justDaniel Dunbar2011-11-041-11/+11
| | | | | | added a layer of indirection with no value (not even conciseness). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143727 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructionsCraig Topper2011-11-041-24/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143683 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r143206, with fixes. Disallow physical register lifetimesDan Gohman2011-11-032-11/+187
| | | | | | | | across calls, and only check for nested dependences on the special call-sequence-resource register. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143660 91177308-0d34-0410-b5e6-96231b3b80d8
* build: Add initial cut at LLVMBuild.txt files.Daniel Dunbar2011-11-037-0/+174
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143634 91177308-0d34-0410-b5e6-96231b3b80d8
* Add new X86 AVX2 VBROADCAST instructions.Craig Topper2011-11-031-13/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143612 91177308-0d34-0410-b5e6-96231b3b80d8
* More AVX2 instructions and intrinsics.Craig Topper2011-11-021-3/+108
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143536 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a bunch more X86 AVX2 instructions and their corresponding intrinsics.Craig Topper2011-11-022-2/+256
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143529 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the x86 backend a couple tricks for dealing with v16i8 sra by a ↵Eli Friedman2011-11-011-0/+18
| | | | | | constant splat value. Fixes PR11289. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143498 91177308-0d34-0410-b5e6-96231b3b80d8
* Begin adding AVX2 instructions. No selection support yet other than intrinsics.Craig Topper2011-10-311-146/+371
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143331 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsics and feature flag for read/write FS/GS base instructions. Also ↵Craig Topper2011-10-305-19/+53
| | | | | | add AVX2 feature flag. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143319 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Emit logical shift by constant splat of <16 x i8> as a <8 x i16> shift ↵Benjamin Kramer2011-10-301-0/+26
| | | | | | and zero out the bits where zeros should've been shifted in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143315 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix pr11266.Nadav Rotem2011-10-301-4/+22
| | | | | | | | | | | On x86: (shl V, 1) -> add V,V Hardware support for vector-shift is sparse and in many cases we scalarize the result. Additionally, on sandybridge padd is faster than shl. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143311 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r143206, as there are still some failing tests.Dan Gohman2011-10-292-187/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143262 91177308-0d34-0410-b5e6-96231b3b80d8
* Reapply r143177 and r143179 (reverting r143188), with schedulerDan Gohman2011-10-282-11/+187
| | | | | | | | | | fixes: Use a separate register, instead of SP, as the calling-convention resource, to avoid spurious conflicts with actual uses of SP. Also, fix unscheduling of calling sequences, which can be triggered by pseudo-two-address dependencies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143206 91177308-0d34-0410-b5e6-96231b3b80d8
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