aboutsummaryrefslogtreecommitdiffstats
path: root/lib/Target/X86
Commit message (Collapse)AuthorAgeFilesLines
...
| * Revert part of a fix from 2010, changes since then:Eric Christopher2013-10-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | a) x86-64 TLS has been documented b) the code path should use movq for the correct relocation to be generated. I've also added a fixme for the test case that we should improve the code generated, it should look something like is documented in the tls abi document. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192631 91177308-0d34-0410-b5e6-96231b3b80d8
| * Reformat this routine slightly.Eric Christopher2013-10-141-10/+8
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192630 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove some extraneous whitespace.Eric Christopher2013-10-141-4/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192629 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fixed a bug in dynamic allocation memory on stack.Elena Demikhovsky2013-10-141-5/+12
| | | | | | | | | | | | | | | | | | The alignment of allocated space was wrong, see Bugzila 17345. Done by Zvi Rackover <zvi.rackover@intel.com>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192573 91177308-0d34-0410-b5e6-96231b3b80d8
| * Create classes to reduce the size of the tablegen entries for the CRC32 ↵Craig Topper2013-10-141-66/+33
| | | | | | | | | | | | instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192568 91177308-0d34-0410-b5e6-96231b3b80d8
| * Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps ↵Craig Topper2013-10-144-83/+102
| | | | | | | | | | | | instructions to parse either GR32 or GR64 without resorting to duplicating instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192567 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add disassembler support for SSE4.1 register/register form of PEXTRW. There ↵Craig Topper2013-10-141-0/+7
| | | | | | | | | | | | is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8
| * Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the ↵Craig Topper2013-10-141-2/+10
| | | | | | | | | | | | disassembler tables. Add PINSRWrr64i to complement the AVX version. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192565 91177308-0d34-0410-b5e6-96231b3b80d8
| * Don't use 64-bit versions of MOVMSKPD in CodeGen. The instructions only ↵Craig Topper2013-10-141-4/+8
| | | | | | | | | | | | produce a 1-bit result so we can just use SUBREG_TO_REG to extend the 32-bit versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192562 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove more filters from the disassembler. Mark some AVX512 instructions as ↵Craig Topper2013-10-121-0/+6
| | | | | | | | | | | | CodeGenOnly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192525 91177308-0d34-0410-b5e6-96231b3b80d8
| * Mark some more instructions as CodeGenOnly. Remove filters from the ↵Craig Topper2013-10-121-17/+19
| | | | | | | | | | | | disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192522 91177308-0d34-0410-b5e6-96231b3b80d8
| * Allow non-AVX form of pmovmskb to take a GR64 operand.Craig Topper2013-10-101-0/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192341 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove duplicate instructions.Craig Topper2013-10-101-16/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192340 91177308-0d34-0410-b5e6-96231b3b80d8
| * AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-093-36/+92
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192283 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add missing HasAVX512 predicate.Andrew Trick2013-10-091-2/+2
| | | | | | | | | | | | | | This was only working because AVX had cheaper rules in all cases. I'm sure there are other places in this file where predicates are missing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192276 91177308-0d34-0410-b5e6-96231b3b80d8
| * Replace a couple instructions with patterns referring to other instructions ↵Craig Topper2013-10-091-16/+11
| | | | | | | | | | | | with same encoding and operands. Mark a couple other instructions as CodeGenOnly since we have FR and VR instructions and only one of them is needed by the assembler/disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192274 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use AVX512PIi8 for the alt forms of vcmp instructions. This adds the TB ↵Craig Topper2013-10-091-4/+4
| | | | | | | | | | | | prefix and keeps the mnemonic from starting with an extra 'v' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192272 91177308-0d34-0410-b5e6-96231b3b80d8
| * Mark some instructions as CodeGenOnly since they aren't needed by the ↵Craig Topper2013-10-091-65/+73
| | | | | | | | | | | | assembler or disassembler. Disassembler already filtered them, but asm parser still had them in its tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192271 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. ↵Craig Topper2013-10-093-8/+12
| | | | | | | | | | | | This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192266 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add a MCTargetStreamer interface.Rafael Espindola2013-10-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove unneeded MMX instruction definition by moving pattern to an ↵Craig Topper2013-10-081-6/+2
| | | | | | | | | | | | equivalent instruction definition and removing the filtering from the disassembler table building. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192175 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove some instructions that existed to provide aliases to the assembler. ↵Craig Topper2013-10-081-27/+10
| | | | | | | | | | | | Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
| * X86: Fix type check. Just because an integer type is illegal doesn't mean ↵Benjamin Kramer2013-10-071-1/+1
| | | | | | | | | | | | | | | | | | it's i64. Fixes PR17495, where an i24 triggered this code. It's intended to optimize i64 loads on 32 bit x86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192123 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove getEHExceptionRegister and getEHHandlerRegister.Rafael Espindola2013-10-072-12/+0
| | | | | | | | | | | | They haven't been used for a long time. Patch by MathOnNapkins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192099 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove some instructions that seem to only exist to trick the filtering ↵Craig Topper2013-10-071-12/+0
| | | | | | | | | | | | checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192090 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove FsMOVAPSrr and friends. They have no patterns and are no longer ↵Craig Topper2013-10-072-29/+4
| | | | | | | | | | | | selected anywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192089 91177308-0d34-0410-b5e6-96231b3b80d8
| * Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to ↵Craig Topper2013-10-072-1/+50
| | | | | | | | | | | | | | | | | | | | register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192088 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add disassembler support for long encodings for INC/DEC in 32-bit mode.Craig Topper2013-10-071-1/+15
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192086 91177308-0d34-0410-b5e6-96231b3b80d8
| * X86: Don't fold spills into SSE operations if the stack is unaligned.Benjamin Kramer2013-10-061-0/+4
| | | | | | | | | | | | | | Regalloc can emit unaligned spills nowadays, but we can't fold the spills into SSE ops if we can't guarantee alignment. PR12250. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192064 91177308-0d34-0410-b5e6-96231b3b80d8
| * AVX-512: added scalar convert instructions and intrinsics.Elena Demikhovsky2013-10-063-13/+189
| | | | | | | | | | | | | | Fixed load folding in VPERM2I instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192063 91177308-0d34-0410-b5e6-96231b3b80d8
| * AVX-512: fixed shuffle loweringElena Demikhovsky2013-10-062-1/+15
| | | | | | | | | | | | | | in case of BLEND and added VSHUFPS patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192055 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add TBM instructions to loading folding tables.Craig Topper2013-10-051-1/+21
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192046 91177308-0d34-0410-b5e6-96231b3b80d8
| * Rename this feature to "cx16" to match gcc's flag name. Apparently these stringsNick Lewycky2013-10-051-1/+1
| | | | | | | | | | | | | | are directly tied to the flag names in clang with no remapping in between? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192044 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove underscores from TBM instruction names for consistency with other ↵Craig Topper2013-10-051-24/+24
| | | | | | | | | | | | instruction naming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192040 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns ↵Craig Topper2013-10-051-39/+20
| | | | | | | | | | | | are sufficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192039 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into ↵Craig Topper2013-10-051-0/+6
| | | | | | | | | | | | (sub -2, x). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192037 91177308-0d34-0410-b5e6-96231b3b80d8
| * AVX-512: Fixed encoding of VMOVQ instruction.Elena Demikhovsky2013-10-031-3/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191889 91177308-0d34-0410-b5e6-96231b3b80d8
| * Replace C++ style comment with a C style comment to satisfy some of the ↵Craig Topper2013-10-031-1/+1
| | | | | | | | | | | | build bots. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191880 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove comma from the end of an enum.Craig Topper2013-10-031-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191877 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add XOP disassembler support. Fixes PR13933.Craig Topper2013-10-035-125/+238
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191874 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add patterns for selecting TBM instructions from logical operations. Patch ↵Craig Topper2013-10-032-32/+98
| | | | | | | | | | | | from Yunzhong Gao. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191871 91177308-0d34-0410-b5e6-96231b3b80d8
| * AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 targetElena Demikhovsky2013-10-022-8/+5
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191818 91177308-0d34-0410-b5e6-96231b3b80d8
| * AVX-512: Added TB prefix to all instructions without prefixes,Elena Demikhovsky2013-10-022-20/+18
| | | | | | | | | | | | | | otherwise encoding fails after the last change in X86MCCodeEmitter.cpp. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191812 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove several unused variables.Rafael Espindola2013-10-012-4/+0
| | | | | | | | | | | | Patch by Alp Toker. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191757 91177308-0d34-0410-b5e6-96231b3b80d8
| * AVX-512: Added X86vzmovl patternsElena Demikhovsky2013-10-011-0/+5
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191733 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove 0 as a valid encoding for the m-mmmm field.Craig Topper2013-10-011-2/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191732 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove unneeded fields from disassembler internal instruction format.Craig Topper2013-10-012-20/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191731 91177308-0d34-0410-b5e6-96231b3b80d8
| * BEXTR should be defined to take same type for bother operands.Craig Topper2013-10-011-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191728 91177308-0d34-0410-b5e6-96231b3b80d8
| * Forgot to add a break statement.Preston Gurd2013-09-301-0/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191715 91177308-0d34-0410-b5e6-96231b3b80d8
| * The X86FixupLEAs pass for Intel Atom must not call convertToThreeAddressPreston Gurd2013-09-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | on ADD16rr opcodes, if src1 != src, since that would cause convertToThreeAddress to try to create a virtual register. This is not permitted after register allocation, which is when the X86FixupLEAs pass runs. This patch fixes PR16785. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191711 91177308-0d34-0410-b5e6-96231b3b80d8
generated by cgit v1.1 at 2025-07-25 08:13:24 +0000