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* The labyrinthine X86 backend no longer appears to requireDan Gohman2011-02-171-37/+0
| | | | | | | these patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125759 91177308-0d34-0410-b5e6-96231b3b80d8
* Triple::MinGW64 is deprecated and removed. We can use Triple::MinGW32 generally.NAKAMURA Takumi2011-02-175-8/+2
| | | | | | No one uses *-mingw64. mingw-w64 is represented as {i686|x86_64}-w64-mingw32. In llvm side, i686 and x64 can be treated as similar way. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125747 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix whitespace.NAKAMURA Takumi2011-02-172-9/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125746 91177308-0d34-0410-b5e6-96231b3b80d8
* This has been implemented.Duncan Sands2011-02-171-10/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125738 91177308-0d34-0410-b5e6-96231b3b80d8
* add some notes on compares + binops. Remove redundant entries.Chris Lattner2011-02-171-20/+47
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125702 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a few missed xforms from GCC PR14753Chris Lattner2011-02-161-0/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125681 91177308-0d34-0410-b5e6-96231b3b80d8
* Swap VT and DebugLoc operands of getExtLoad() for consistency withStuart Hastings2011-02-166-9/+9
| | | | | | | other getNode() methods. Radar 9002173. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125665 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove outdated README entry.Eli Friedman2011-02-161-12/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125660 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove outdated README entry.Eli Friedman2011-02-161-16/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125659 91177308-0d34-0410-b5e6-96231b3b80d8
* Update README entry.Eli Friedman2011-02-161-13/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125658 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for pushsection and popsection. Patch by Joerg Sonnenberger.Rafael Espindola2011-02-161-12/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125629 91177308-0d34-0410-b5e6-96231b3b80d8
* Some single precision VFP instructions may be executed on NEON pipeline, but ↵Evan Cheng2011-02-162-28/+160
| | | | | | not double precision ones. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125624 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach ARMLoadStoreOptimizer to remove kill flags from merged instructions as ↵Jakob Stoklund Olesen2011-02-151-21/+15
| | | | | | | | | | | | | | | | | | | | | | | | | well. This is necessary to avoid a crash in certain tangled situations where a kill flag is first correctly moved to a merged instruction, and then needs to be moved again: STR %R0, a... STR %R0<kill>, b... First becomes: STR %R0, b... STM a, %R0<kill>, ... and then: STM a, %R0, ... STM b, %R0<kill>, ... We can now remove the kill flag from the merged STM when needed. 8960050. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125591 91177308-0d34-0410-b5e6-96231b3b80d8
* Spelling fix: consequtive -> consecutive.Duncan Sands2011-02-151-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125563 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unused bitvectors that record ARM callee-saved registers.Bob Wilson2011-02-142-23/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125534 91177308-0d34-0410-b5e6-96231b3b80d8
* A fail to match coprocessor number and register number must fail instead of ↵Bruno Cardoso Lopes2011-02-141-1/+0
| | | | | | assert. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125521 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix encoding and add parsing support for the arm/thumb CPS instruction:Bruno Cardoso Lopes2011-02-1410-109/+276
| | | | | | | | | | | | | | - Add custom operand matching for imod and iflags. - Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC from mnemonic. - While adding ".w" as an operand, don't change "Head" to avoid passing the wrong mnemonic to ParseOperand. - Add asm parser tests. - Add disassembler tests just to make sure it can catch all cps versions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
* Enhance ComputeMaskedBits to know that aligned frameindexesChris Lattner2011-02-133-63/+54
| | | | | | | | | | | | | | | | | | | have their low bits set to zero. This allows us to optimize out explicit stack alignment code like in stack-align.ll:test4 when it is redundant. Doing this causes the code generator to start turning FI+cst into FI|cst all over the place, which is general goodness (that is the canonical form) except that various pieces of the code generator don't handle OR aggressively. Fix this by introducing a new SelectionDAG::isBaseWithConstantOffset predicate, and using it in places that are looking for ADD(X,CST). The ARM backend in particular was missing a lot of addressing mode folding opportunities around OR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125470 91177308-0d34-0410-b5e6-96231b3b80d8
* Add encodings and mnemonics for FXSAVE64 and FXRSTOR64.Reid Kleckner2011-02-121-0/+4
| | | | | | | | | These are just FXSAVE and FXRSTOR with REX.W prefixes. These versions use 64-bit pointer values instead of 32-bit pointer values in the memory map they dump and restore. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125446 91177308-0d34-0410-b5e6-96231b3b80d8
* Prevent IMPLICIT_DEF/KILL to become a delay filler instruction in SPARC backend.Venkatraman Govindaraju2011-02-121-0/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125444 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a note about SSE4.1 roundss/roundsd.Benjamin Kramer2011-02-121-0/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125438 91177308-0d34-0410-b5e6-96231b3b80d8
* AsmMatcher custom operand parser failure enhancements.Jim Grosbach2011-02-123-23/+32
| | | | | | | | | | | | | Teach the AsmMatcher handling to distinguish between an error custom-parsing an operand and a failure to match. The former should propogate the error upwards, while the latter should continue attempting to parse with alternative matchers. Update the ARM asm parser accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125426 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement sdiv & udiv for <4 x i16> and <8 x i8> NEON vector types.Nate Begeman2011-02-111-0/+182
| | | | | | | This avoids moving each element to the integer register file and calling __divsi3 etc. on it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125402 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove std::string version of getNameWithPrefix.Rafael Espindola2011-02-111-10/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125363 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix buggy fcopysign lowering.Evan Cheng2011-02-111-5/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This define float @foo(float %x, float %y) nounwind readnone { entry: %0 = tail call float @copysignf(float %x, float %y) nounwind readnone ret float %0 } Was compiled to: vmov s0, r1 bic r0, r0, #-2147483648 vmov s1, r0 vcmpe.f32 s0, #0 vmrs apsr_nzcv, fpscr it lt vneglt.f32 s1, s1 vmov r0, s1 bx lr This fails to copy the sign of -0.0f because it's lost during the float to int conversion. Also, it's sub-optimal when the inputs are in GPR registers. Now it uses integer and + or operations when it's profitable. And it's correct! lsrs r1, r1, #31 bfi r0, r1, #31, #1 bx lr rdar://8984306 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125357 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Implement 256-bit vector lowering for SCALAR_TO_VECTOR. ThisDavid Greene2011-02-101-0/+18
| | | | | | | | largely completes support for 128-bit fallback lowering for code that is not 256-bit ready. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125315 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a lot of o32 CC issues and add a bunch of tests. Patch by Akira Hatanaka ↵Bruno Cardoso Lopes2011-02-101-47/+71
| | | | | | with some small modifications by me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125292 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Implement 256-bit vector lowering for EXTRACT_VECTOR_ELT.David Greene2011-02-101-1/+35
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125284 91177308-0d34-0410-b5e6-96231b3b80d8
* ptx: add passing parameter to kernel functionsChe-Liang Chiou2011-02-108-61/+96
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125279 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Implement 256-bit vector lowering for INSERT_VECTOR_ELT.David Greene2011-02-091-6/+36
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125187 91177308-0d34-0410-b5e6-96231b3b80d8
* Add intrinsic for setc instruction on the XCore.Richard Osborne2011-02-091-1/+12
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125186 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 ↵Owen Anderson2011-02-088-128/+86
| | | | | | (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125127 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Implement BUILD_VECTOR lowering for 256-bit vectors. ForDavid Greene2011-02-081-3/+64
| | | | | | | | anything but the simplest of cases, lower a 256-bit BUILD_VECTOR by splitting it into 128-bit parts and recombining. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125105 91177308-0d34-0410-b5e6-96231b3b80d8
* Temporary workaround for a bad bug introduced by r121082 which replacedEvan Cheng2011-02-082-8/+19
| | | | | | | | | | | | | t2LDRpci with t2LDRi12. There are a couple of problems with this. 1. The encoding for the literal and immediate constant are different. Note bit 7 of the literal case is 'U' so it can be negative. 2. t2LDRi12 is now narrowed to tLDRpci before constant island pass is run. So we end up never using the Thumb2 instruction, which ends up creating a lot more constant islands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125074 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for parsing dmb/dsb instructionsBruno Cardoso Lopes2011-02-073-0/+65
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125055 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove the MCR asm parser hack and start using the custom target specific asmBruno Cardoso Lopes2011-02-072-31/+106
| | | | | | | | | | | | | | | | | | | | | parsing of operands introduced in r125030. As a small note, besides using a more generic approach we can also have more descriptive output when debugging llvm-mc, example: mcr p7, #1, r5, c1, c1, #4 note: parsed instruction: ['mcr', <ARMCC::al>, <coprocessor number: 7>, 1, <register 73>, <coprocessor register: 1>, <coprocessor register: 1>, 4] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125052 91177308-0d34-0410-b5e6-96231b3b80d8
* [AVX] Insert/extract subvector lowering support. This includes aDavid Greene2011-02-071-2/+101
| | | | | | | | couple of utility functions that will be used in other places for more AVX lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125029 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM/MC/ELF Lowercase .cpu attributes in .s, but make them uppercase in .oJason W Kim2011-02-071-3/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125025 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix an obvious typo which caused an isel assertion. rdar://8964854.Evan Cheng2011-02-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125023 91177308-0d34-0410-b5e6-96231b3b80d8
* Add codegen support for using post-increment NEON load/store instructions.Bob Wilson2011-02-073-145/+546
| | | | | | | | The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using post-increment versions, but all the rest of the NEON load/store instructions should be handled now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125014 91177308-0d34-0410-b5e6-96231b3b80d8
* Change VLD3/4 and VST3/4 for quad registers to not update the address register.Bob Wilson2011-02-073-65/+89
| | | | | | | | | | | | These operations are expanded to pairs of loads or stores, and the first one uses the address register update to produce the address for the second one. So far, the second load/store has also updated the address register, just for convenience, since that output has never been used. In anticipation of actually supporting post-increment updates for these operations, this changes the non-updating operations to use a non-updating load/store for the second instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125013 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix some NEON instruction itineraries.Bob Wilson2011-02-071-12/+16
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125012 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a comment: addrmode6 no longer includes the optional writeback flag.Bob Wilson2011-02-071-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125011 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove inaccurate comments: so_imm and t2_so_imm operands are not encodedBob Wilson2011-02-072-8/+2
| | | | | | until the instructions are emitted or printed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125010 91177308-0d34-0410-b5e6-96231b3b80d8
* Move code for OffsetCompare struct closer to where it is used.Bob Wilson2011-02-071-11/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125009 91177308-0d34-0410-b5e6-96231b3b80d8
* Rework some .ARM.attribute work for improved gcc compatibility.Jason W Kim2011-02-072-13/+84
| | | | | | | | | Unified EmitTextAttribute for both Asm and Obj emission (.cpu only) Added necessary cortex-A8 related attrs for codegen compat tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124995 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove a virtual inheritance case that clang can devirtualize fully now.Anders Carlsson2011-02-061-21/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124989 91177308-0d34-0410-b5e6-96231b3b80d8
* Target/X86: Tweak allocating shadow area (aka home) on Win64. It must be ↵NAKAMURA Takumi2011-02-053-9/+20
| | | | | | enough for caller to allocate one. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124949 91177308-0d34-0410-b5e6-96231b3b80d8
* lib/Target/X86/X86ISelLowering.cpp: Introduce a new variable "IsWin64". No ↵NAKAMURA Takumi2011-02-051-3/+4
| | | | | | functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124948 91177308-0d34-0410-b5e6-96231b3b80d8
* lib/Target/X86/X86JITInfo.cpp: Add Win64 stuff.NAKAMURA Takumi2011-02-051-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124947 91177308-0d34-0410-b5e6-96231b3b80d8
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