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* When adding the carry bit to another value on X86, exploit the fact that the ↵Owen Anderson2010-09-211-0/+23
| | | | | | | | | | | | carry-materialization (sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold the intermediate AND and the ADD into a single SUB. This fixes <rdar://problem/8449754>. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114460 91177308-0d34-0410-b5e6-96231b3b80d8
* Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON loadBob Wilson2010-09-212-0/+64
| | | | | | | and store intrinsics are represented with MemIntrinsicSDNodes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114454 91177308-0d34-0410-b5e6-96231b3b80d8
* eliminate some uses of the getStore overload.Chris Lattner2010-09-213-41/+60
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114453 91177308-0d34-0410-b5e6-96231b3b80d8
* eliminate an old SelectionDAG::getTruncStore method, propagatingChris Lattner2010-09-213-10/+14
| | | | | | | MachinePointerInfo around more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114452 91177308-0d34-0410-b5e6-96231b3b80d8
* propagate MachinePointerInfo through various uses of the oldChris Lattner2010-09-215-36/+38
| | | | | | | SelectionDAG::getExtLoad overload, and eliminate it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114446 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix errant printing of [v]ldm instructions that aren't a popJim Grosbach2010-09-211-32/+24
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114445 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix buglet when the TST instruction directly uses the AND result.Gabor Greif2010-09-211-5/+6
| | | | | | | I am unable to write a test for this case, help is solicited, though... What I did is to tickle the code in the debugger and verify that we do the right thing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114430 91177308-0d34-0410-b5e6-96231b3b80d8
* Move the search for the appropriate AND instructionGabor Greif2010-09-212-20/+44
| | | | | | | | | | | into OptimizeCompareInstr. This necessitates the passing of CmpValue around, so widen the virtual functions to accomodate. No functionality changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114428 91177308-0d34-0410-b5e6-96231b3b80d8
* convert the targets off the non-MachinePointerInfo of getLoad.Chris Lattner2010-09-2111-102/+116
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114410 91177308-0d34-0410-b5e6-96231b3b80d8
* it's more elegant to put the "getConstantPool" andChris Lattner2010-09-214-29/+28
| | | | | | | | | "getFixedStack" on the MachinePointerInfo class. While this isn't the problem I'm setting out to solve, it is the right way to eliminate PseudoSourceValue, so lets go with it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114406 91177308-0d34-0410-b5e6-96231b3b80d8
* update the X86 backend to use the MachinePointerInfo version of oneChris Lattner2010-09-211-38/+44
| | | | | | | | of the getLoad methods. This fixes at least one bug where an incorrect svoffset is passed in (a potential combiner-aa miscompile). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114404 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix a bug where the x86 backend would lower memcpy/memset of segment ↵Chris Lattner2010-09-211-0/+9
| | | | | | | | | relative operations into non-segment-relative copies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114402 91177308-0d34-0410-b5e6-96231b3b80d8
* reimplement memcpy/memmove/memset lowering to use MachinePointerInfoChris Lattner2010-09-218-37/+31
| | | | | | | | instead of srcvalue/offset pairs. This corrects SV info for mem operations whose size is > 32-bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114401 91177308-0d34-0410-b5e6-96231b3b80d8
* convert targets to the new MF.getMachineMemOperand interface.Chris Lattner2010-09-219-30/+42
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114391 91177308-0d34-0410-b5e6-96231b3b80d8
* fix rdar://8453210, a crash handling a call through a GS relative load.Chris Lattner2010-09-211-1/+7
| | | | | | | For now, just disable folding the load into the call. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114386 91177308-0d34-0410-b5e6-96231b3b80d8
* Simplify ARM callee-saved register handling by removing the distinctionJim Grosbach2010-09-203-167/+59
| | | | | | | | | | | | | | | | | | | | | between the high and low registers for prologue/epilogue code. This was a Darwin-only thing that wasn't providing a realistic benefit anymore. Combining the save areas simplifies the compiler code and results in better ARM/Thumb2 codegen. For example, previously we would generate code like: push {r4, r5, r6, r7, lr} add r7, sp, #12 stmdb sp!, {r8, r10, r11} With this change, we combine the register saves and generate: push {r4, r5, r6, r7, r8, r10, r11, lr} add r7, sp, #12 rdar://8445635 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114340 91177308-0d34-0410-b5e6-96231b3b80d8
* idiom recognition should catch this.Chris Lattner2010-09-191-0/+32
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114304 91177308-0d34-0410-b5e6-96231b3b80d8
* add a readme.Chris Lattner2010-09-191-0/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114303 91177308-0d34-0410-b5e6-96231b3b80d8
* X86Subtarget.h: Fix Cygwin's TD.NAKAMURA Takumi2010-09-181-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114297 91177308-0d34-0410-b5e6-96231b3b80d8
* Add the exit instruction to the PTX target.Eric Christopher2010-09-1822-16/+705
| | | | | | | Patch by Che-Liang Chiou <clchiou@gmail.com>! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114294 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix build.Michael J. Spencer2010-09-181-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114292 91177308-0d34-0410-b5e6-96231b3b80d8
* Thumb opcodes for thumb calls.Eric Christopher2010-09-181-1/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114263 91177308-0d34-0410-b5e6-96231b3b80d8
* Add addrmode5 fp load support. Swap float/thumb operand adding to handleEric Christopher2010-09-181-5/+21
| | | | | | | thumb with floating point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114256 91177308-0d34-0410-b5e6-96231b3b80d8
* Floating point stores have a 3rd addressing mode type.Eric Christopher2010-09-181-1/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114254 91177308-0d34-0410-b5e6-96231b3b80d8
* factor out a simple helper function to create a label for PC-relativeJim Grosbach2010-09-181-19/+17
| | | | | | instructions (PICADD, PICLDR, et.al.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114243 91177308-0d34-0410-b5e6-96231b3b80d8
* PC-relative pseudo instructions are lowered and printed directly. Any encounterJim Grosbach2010-09-181-3/+2
| | | | | | with one in the generic printing code is an error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114242 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix vmov.f64 disassembly on targets where sizeof(long) != 8.Benjamin Kramer2010-09-171-2/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114240 91177308-0d34-0410-b5e6-96231b3b80d8
* Add MC-inst handling for tPICADDJim Grosbach2010-09-171-0/+26
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114237 91177308-0d34-0410-b5e6-96231b3b80d8
* Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64Bob Wilson2010-09-171-0/+27
| | | | | | | | | value should be in GPRs when it's going to be used as a scalar, and we use VMOVRRD to make that happen, but if the value is converted back to a vector we need to fold to a simple bit_convert. Radar 8407927. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114233 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach the (non-MC) instruction printer to use the cannonical names for push/pop,Jim Grosbach2010-09-172-4/+72
| | | | | | and shift instructions on ARM. Update the tests to match. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114230 91177308-0d34-0410-b5e6-96231b3b80d8
* Rework arm fast isel branch and compare code.Eric Christopher2010-09-171-8/+70
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114226 91177308-0d34-0410-b5e6-96231b3b80d8
* Hook up verbose asm comment printing for SOImm operands in MC printerJim Grosbach2010-09-173-8/+6
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114215 91177308-0d34-0410-b5e6-96231b3b80d8
* trailing whitespaceJim Grosbach2010-09-171-8/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114212 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid emitting a PIC base register if no PIC addresses are needed.Dan Gohman2010-09-171-2/+8
| | | | | | | This fixes rdar://8396318. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114201 91177308-0d34-0410-b5e6-96231b3b80d8
* Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!Jim Grosbach2010-09-173-0/+120
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114195 91177308-0d34-0410-b5e6-96231b3b80d8
* handle the upper16/lower16 target operand flags on symbol references for MCJim Grosbach2010-09-175-23/+60
| | | | | | instruction lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114191 91177308-0d34-0410-b5e6-96231b3b80d8
* fix rdar://8444631 - encoder crash on 'enter'Chris Lattner2010-09-174-4/+18
| | | | | | | What a weird instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114190 91177308-0d34-0410-b5e6-96231b3b80d8
* expand PICLDR MC lowering to handle other PICLDR and PICSTR versions.Jim Grosbach2010-09-171-11/+31
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114183 91177308-0d34-0410-b5e6-96231b3b80d8
* AlphaSchedule.td: 7bit-ize.NAKAMURA Takumi2010-09-171-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114173 91177308-0d34-0410-b5e6-96231b3b80d8
* fix rdar://8438816 - unrecognized 'fildq' instructionChris Lattner2010-09-161-1/+2
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114116 91177308-0d34-0410-b5e6-96231b3b80d8
* MC-ization of the PICLDR pseudo. Next up, adding the other variantsJim Grosbach2010-09-162-1/+33
| | | | | | (PICLDRB, et. al.) and PICSTR* git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114098 91177308-0d34-0410-b5e6-96231b3b80d8
* Make sure to promote single precision floats to double before extracting themJim Grosbach2010-09-161-2/+4
| | | | | | from the APFloat. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114096 91177308-0d34-0410-b5e6-96231b3b80d8
* Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.Kalle Raiskila2010-09-163-238/+177
| | | | | | | | | | | | | | This cleans up after the mess r108567 left in the CellSPU backend. ORCvt-instruction were used to reinterpret registers, and the ORs were then removed by isMoveInstr(). This patch now removes 350 instrucions of format: or $3, $3, $3 (from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is checked for. Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114074 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove support for "dregpair" operand modifier, now that it is no longer beingBob Wilson2010-09-162-36/+2
| | | | | | | used for anything. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114067 91177308-0d34-0410-b5e6-96231b3b80d8
* When expanding ARM pseudo registers, copy the existing predicate operandsBob Wilson2010-09-161-9/+29
| | | | | | | instead of using default predicates on the expanded instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114066 91177308-0d34-0410-b5e6-96231b3b80d8
* store MC FP immediates as a double instead of as an APFloat, thus avoiding anJim Grosbach2010-09-163-4/+8
| | | | | | unnecessary dtor for MCOperand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114064 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing break.Bob Wilson2010-09-161-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114048 91177308-0d34-0410-b5e6-96231b3b80d8
* Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded afterBob Wilson2010-09-163-15/+70
| | | | | | | | register allocation to VLDMD and VSTMD respectively. This avoids using the dregpair operand modifier. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114047 91177308-0d34-0410-b5e6-96231b3b80d8
* Add support for the 'lane' modifier on vdup operandsJim Grosbach2010-09-151-7/+25
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114030 91177308-0d34-0410-b5e6-96231b3b80d8
* Remember VLDMQ.Jakob Stoklund Olesen2010-09-151-0/+9
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114026 91177308-0d34-0410-b5e6-96231b3b80d8
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