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* Update build rules for LLVM merge to version 176139.Stephen Hines2013-03-051-1/+3
| | | | Change-Id: Ibb71ad9a6a2ed05dbf87f249ac42b1355e3fa41a
* Merge commit 'b3201c5cf1e183d840f7c99ff779d57f1549d8e5' into merge_20130226Stephen Hines2013-03-05370-11923/+40649
|\ | | | | | | | | | | | | | | Conflicts: include/llvm/Support/ELF.h lib/Support/DeltaAlgorithm.cpp Change-Id: I24a4fbce62eb39d924efee3c687b55e1e17b30cd
| * Fix PR15332 (patch by Florian Zeitz).Bill Schmidt2013-02-261-4/+5
| | | | | | | | | | | | | | | | | | | | There's no need to generate a stack frame for PPC32 SVR4 when there are no local variables assigned to the stack, i.e., when no red zone is needed. (PPC64 supports a red zone, but PPC32 does not.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176124 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Add promotion of e32 to e64 in operand foldingChristian Konig2013-02-261-2/+34
| | | | | | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176105 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: add VOP mapping functionsChristian Konig2013-02-263-11/+35
| | | | | | | | | | | | | | | | | | Make it possible to map between e32 and e64 encoding opcodes. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176104 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: swap operands if it helps foldingChristian Konig2013-02-261-1/+15
| | | | | | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176103 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: add some more instruction flagsChristian Konig2013-02-263-14/+92
| | | | | | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176102 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: add post ISel folding for SI v2Christian Konig2013-02-265-23/+231
| | | | | | | | | | | | | | | | | | | | | | Include immediate folding and SGPR limit handling for VOP3 instructions. v2: remove leftover hasExtraSrcRegAllocReq Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176101 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: add folding helperChristian Konig2013-02-264-0/+30
| | | | | | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176100 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: fix VOP3b encoding v2Christian Konig2013-02-262-6/+32
| | | | | | | | | | | | | | | | | | | | | | v2: document why we hardcode VCC for now. This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176099 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: fix and cleanup SI register definition v2Christian Konig2013-02-262-97/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prevent producing real strange tablegen code by using proper register sizes, alignments and hierarchy. Also cleanup the unused definitions and add some comments. v2: add SGPR 512 bit registers, stop registers from wrapping around, fix SGPR alignment This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176098 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: fix stupid typoChristian Konig2013-02-261-1/+1
| | | | | | | | | | | | | | | | | | This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176097 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Use class RegDefsUses to track register defs and uses.Akira Hatanaka2013-02-261-89/+82
| | | | | | | | | | | | | | No functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176070 91177308-0d34-0410-b5e6-96231b3b80d8
| * [fast-isel] Make sure the FastLowerArguments function checks to make sure theChad Rosier2013-02-262-0/+2
| | | | | | | | | | | | | | arguments type is a simple type. rdar://13290455 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176066 91177308-0d34-0410-b5e6-96231b3b80d8
| * Refine fix to PR10499, no functionality changeMichael Liao2013-02-251-1/+1
| | | | | | | | | | | | | | | | - Put expensive checking after simple one git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176060 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix PR10499Michael Liao2013-02-251-1/+1
| | | | | | | | | | | | | | | | | | - Check whether SSE is available before lowering all 1s vector building with PCMPEQD, which is only available from SSE2 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176058 91177308-0d34-0410-b5e6-96231b3b80d8
| * [fast-isel] Add X86FastIsel::FastLowerArguments to handle functions with 6 orChad Rosier2013-02-251-0/+73
| | | | | | | | | | | | | | | | | | | | fewer scalar integer (i32 or i64) arguments. It completely eliminates the need for SDISel for trivial functions. Also, add the new llc -fast-isel-abort-args option, which is similar to -fast-isel-abort option, but for formal argument lowering. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176052 91177308-0d34-0410-b5e6-96231b3b80d8
| * [ms-inline asm] Add support for the pushad/popad mnemonics.Chad Rosier2013-02-251-4/+2
| | | | | | | | | | | | rdar://13254235 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176036 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix missing relocation for TLS addressing peephole optimization.Bill Schmidt2013-02-251-0/+3
| | | | | | | | | | | | | | Report and fix due to Kai Nacke. Testcase update by me. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176029 91177308-0d34-0410-b5e6-96231b3b80d8
| * Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.Reed Kotler2013-02-255-69/+70
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176007 91177308-0d34-0410-b5e6-96231b3b80d8
| * Make psuedo FEXT_T8I816_ins into a custom emitter.Reed Kotler2013-02-245-61/+39
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176002 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix PR14364.Bill Schmidt2013-02-244-20/+27
| | | | | | | | | | | | | | | | | | | | | | | | This removes a const_cast hack from PPCRegisterInfo::hasReservedSpillSlot(). The proper place to save the frame index for the CR spill slot is in the PPCFunctionInfo object, not the PPCRegisterInfo object. No new test cases, as this just reimplements existing function. Existing tests such as test/CodeGen/PowerPC/crsave.ll are sufficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175998 91177308-0d34-0410-b5e6-96231b3b80d8
| * TypoFrancois Pichet2013-02-241-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175991 91177308-0d34-0410-b5e6-96231b3b80d8
| * Revert r169638 because it broke Mesa llvmpipe tests.Nadav Rotem2013-02-241-6/+1
| | | | | | | | | | | | | | | | Fix PR15239. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175985 91177308-0d34-0410-b5e6-96231b3b80d8
| * Make psuedo FEXT_T8I816_ins a custom inserter. It should be expandedReed Kotler2013-02-244-22/+34
| | | | | | | | | | | | | | | | as early as possible; which means during instruction selection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175984 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add new base instruction def for cmpi, cmp, slt and sltu so that def/usesReed Kotler2013-02-231-5/+10
| | | | | | | | | | | | | | | | proper. Fixed this already a few days ago for slti. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175975 91177308-0d34-0410-b5e6-96231b3b80d8
| * X86: Disable cmov-memory patterns on subtargets without cmov.Benjamin Kramer2013-02-231-6/+8
| | | | | | | | | | | | Fixes PR15115. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175962 91177308-0d34-0410-b5e6-96231b3b80d8
| * Expand pseudos/macros for Selt. This is the last of the complexReed Kotler2013-02-233-0/+82
| | | | | | | | | | | | | | | | macros.The rest is some small misc. stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175950 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARM: Convenience aliases for 'srs*' instructions.Jim Grosbach2013-02-233-0/+28
| | | | | | | | | | | | | | | | Handle an implied 'sp' operand. rdar://11466783 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175940 91177308-0d34-0410-b5e6-96231b3b80d8
| * [mips] Emit call16 operator instead of got_disp. The former allows lazy binding.Akira Hatanaka2013-02-221-3/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175920 91177308-0d34-0410-b5e6-96231b3b80d8
| * x86_64: designate most general purpose and SSE registers as callee save ↵Peter Collingbourne2013-02-222-21/+28
| | | | | | | | | | | | under coldcc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175911 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Add pattern for sign extension of i1 to i32.Michel Danzer2013-02-221-0/+5
| | | | | | | | | | | | | | | | | | | | 16 more little piglits with radeonsi. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175887 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Add pattern for logical or of i1 values.Michel Danzer2013-02-221-0/+4
| | | | | | | | | | | | | | | | | | | | 24 more little piglits with radeonsi. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175886 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: Add pattern for fceil.Michel Danzer2013-02-221-1/+3
| | | | | | | | | | | | | | | | | | | | 9 more little piglits with radeonsi. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175885 91177308-0d34-0410-b5e6-96231b3b80d8
| * Make ARMAsmPrinter generate the correct alignment specifier syntax in ↵Kristof Beyls2013-02-221-2/+1
| | | | | | | | | | | | | | | | | | | | | | instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175884 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix a nomenclature mistake. Slt->Slti in the functions. The "i" refersReed Kotler2013-02-222-8/+8
| | | | | | | | | | | | | | | | to the immediate operand of sli or cmp function. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175865 91177308-0d34-0410-b5e6-96231b3b80d8
| * Expand mips16 SelT form pseudso/macros.Reed Kotler2013-02-223-0/+81
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175862 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove code copied from GenRegisterInfo.inc.Andrew Trick2013-02-222-57/+0
| | | | | | | | | | | | | | | | There's no apparent reason this code was copied from generated source into a .cpp. It sets a bad example for those working on other targets and trying to understand the register info API. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175849 91177308-0d34-0410-b5e6-96231b3b80d8
| * Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-2153-569/+541
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175788 91177308-0d34-0410-b5e6-96231b3b80d8
| * Hexagon: Expand cttz, ctlz, and ctpop for now.Anshuman Dasgupta2013-02-211-0/+5
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175783 91177308-0d34-0410-b5e6-96231b3b80d8
| * Radar numbers don't belong in source code.Evan Cheng2013-02-213-4/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175775 91177308-0d34-0410-b5e6-96231b3b80d8
| * Trivial cleanupBill Schmidt2013-02-211-2/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175771 91177308-0d34-0410-b5e6-96231b3b80d8
| * Large code model support for PowerPC.Bill Schmidt2013-02-215-15/+20
| | | | | | | | | | | | | | | | | | | | | | | | Large code model is identical to medium code model except that the addis/addi sequence for "local" accesses is never used. All accesses use the addis/ld sequence. The coding changes are straightforward; most of the patch is taken up with creating variants of the medium model tests for large model. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175767 91177308-0d34-0410-b5e6-96231b3b80d8
| * getX86SubSuperRegister has a special mode with High=true for i64 whichEli Bendersky2013-02-211-17/+9
| | | | | | | | | | | | | | | | | | | | | | | | exists solely to enable it to call itself for i8 with some registers. The proposed patch simplifies the function somewhat to make the High bit only meaningful for the i8 mode, which makes sense. No functional difference (getX86SubSuperRegister is not getting called from anywhere outside with i64 and High=true). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175762 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: inline V_ADD|SUB_F32 patternsChristian Konig2013-02-211-9/+5
| | | | | | | | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175758 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: replace IMPLICIT_DEF with SIOperand.ZEROChristian Konig2013-02-211-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175757 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: replace SI_V_CNDLT with a patternChristian Konig2013-02-213-31/+5
| | | | | | | | | | | | | | | | | | | | | | | | It actually fixes quite a bunch of piglit tests. This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175756 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: use patterns for clamp, fabs, fnegChristian Konig2013-02-212-40/+22
| | | | | | | | | | | | | | | | | | | | | | Instead of using custom inserters, it's simpler and should make DAG folding easier. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175755 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: add all the other missing asm operands v2Christian Konig2013-02-212-22/+29
| | | | | | | | | | | | | | | | | | | | v2: put implicit parameters in [] Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175754 91177308-0d34-0410-b5e6-96231b3b80d8
| * R600/SI: add the missing M*BUF|IMG asm operandsChristian Konig2013-02-211-4/+8
| | | | | | | | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175753 91177308-0d34-0410-b5e6-96231b3b80d8
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