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* [fast-isel] Add support for ADDs with non-legal types.Chad Rosier2012-02-061-5/+34
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149934 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TargetPassConfig to the PassManager for use inside passesAndrew Trick2012-02-061-3/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149926 91177308-0d34-0410-b5e6-96231b3b80d8
* Enable streaming of bitcodeDerek Schuff2012-02-065-8/+8
| | | | | | | | | This CL delays reading of function bodies from initial parse until materialization, allowing overlap of compilation with bitcode download. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149918 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some dead code and tidy things up now that vectors use ConstantDataVectorChris Lattner2012-02-062-25/+4
| | | | | | | | instead of always using ConstantVector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149912 91177308-0d34-0410-b5e6-96231b3b80d8
* [unwind removal] We no longer have 'unwind' instructions being generated, soBill Wendling2012-02-062-8/+0
| | | | | | | remove the code that handles them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149901 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Don't call malloc for 4 bits. No functionality change.Benjamin Kramer2012-02-061-4/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149866 91177308-0d34-0410-b5e6-96231b3b80d8
* Hexagon: Remove forbidden iostream includes (it introduces static initializers)Benjamin Kramer2012-02-068-73/+46
| | | | | | Reorder includes while at it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149863 91177308-0d34-0410-b5e6-96231b3b80d8
* Add shuffle decoding support for 256-bit pshufd. Merge vpermilp* and pshufd ↵Craig Topper2012-02-064-84/+70
| | | | | | decoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149859 91177308-0d34-0410-b5e6-96231b3b80d8
* DefinesPredicate should only look for def operands. Patch by Ludwig Meier.Evan Cheng2012-02-051-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149846 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove dead test: this was already checked and handled a few linesDuncan Sands2012-02-051-5/+0
| | | | | | | above. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149841 91177308-0d34-0410-b5e6-96231b3b80d8
* Persuade GCC that there is nothing worth warning about here (there isn't).Duncan Sands2012-02-053-2/+3
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149834 91177308-0d34-0410-b5e6-96231b3b80d8
* Don't initialize CV in terms of itself! Spotted by GCC.Duncan Sands2012-02-051-4/+4
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149833 91177308-0d34-0410-b5e6-96231b3b80d8
* Begin fleshing out more convenience predicates in llvm::Triple andChandler Carruth2012-02-051-17/+7
| | | | | | | | | | convert at least one client over to use them. Subsequent patches both to LLVM and Clang will try to convert more people over to a common set of predicates. This round of predicates is focused on OS-categorization predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149815 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert assert(0) to llvm_unreachableCraig Topper2012-02-058-0/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149814 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert assert(0) to llvm_unreachable in X86 Target directory.Craig Topper2012-02-058-22/+20
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149809 91177308-0d34-0410-b5e6-96231b3b80d8
* Convert some assert(0) in default of switch statements to llvm_unreachable.Craig Topper2012-02-051-10/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149808 91177308-0d34-0410-b5e6-96231b3b80d8
* Add target specific node for PMULUDQ. Change patterns to use it and custom ↵Craig Topper2012-02-054-69/+69
| | | | | | lower intrinsics to it. Use it instead of intrinsic to handle 64-bit vector multiplies. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149807 91177308-0d34-0410-b5e6-96231b3b80d8
* reapply the patches reverted in r149470 that reenable ConstantDataArray,Chris Lattner2012-02-052-96/+25
| | | | | | | | | | | but with a critical fix to the SelectionDAG code that optimizes copies from strings into immediate stores: the previous code was stopping reading string data at the first nul. Address this by adding a new argument to llvm::getConstantStringInfo, preserving the behavior before the patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149800 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove most of the intrinsics for XOP VPCMOV instruction. They all aliased ↵Craig Topper2012-02-051-125/+0
| | | | | | to the same instruction with different types. This would be better accomplished with casts in the not yet created xopintrin.h header file. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149795 91177308-0d34-0410-b5e6-96231b3b80d8
* TargetPassConfig: confine the MC configuration to TargetMachine.Andrew Trick2012-02-0422-87/+62
| | | | | | | | | | Passes prior to instructon selection are now split into separate configurable stages. Header dependencies are simplified. The bulk of this diff is simply removal of the silly DisableVerify flags. Sorry for the target header churn. Attempting to stabilize them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149754 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Add support for URem.Chad Rosier2012-02-031-8/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149716 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Rename isZExt to isSigned. No functional change intended.Chad Rosier2012-02-031-13/+14
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149714 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Add support for UDIV.Chad Rosier2012-02-031-8/+10
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149712 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Add support for FPToUI. Also add test cases for FPToSI.Chad Rosier2012-02-031-6/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149706 91177308-0d34-0410-b5e6-96231b3b80d8
* [fast-isel] Add support for selecting UIToFP.Chad Rosier2012-02-031-6/+8
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149704 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove getShuffleVPERMILPImmediate function, getShuffleSHUFImmediate ↵Craig Topper2012-02-031-30/+1
| | | | | | performs the same calculation. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149683 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unnecessary qualification on 256-bit vector handling in ↵Craig Topper2012-02-031-2/+2
| | | | | | LowerBUILD_VECTOR. Condition was already guaranteed by earlier code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149680 91177308-0d34-0410-b5e6-96231b3b80d8
* Added TargetPassConfig. The first little step toward configuring codegen passes.Andrew Trick2012-02-0322-154/+401
| | | | | | | | | | | Allows command line overrides to be centralized in LLVMTargetMachine.cpp. LLVMTargetMachine can intercept common passes and give precedence to command line overrides. Allows adding "internal" target configuration options without touching TargetOptions. Encapsulates the PassManager. Provides a good point to initialize all CodeGen passes so that Pass ID's can be used in APIs. Allows modifying the target configuration hooks without rebuilding the world. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149672 91177308-0d34-0410-b5e6-96231b3b80d8
* whitespaceAndrew Trick2012-02-034-15/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149671 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a new MachineJumpTableInfo entry type, EK_GPRel64BlockAddress, which isAkira Hatanaka2012-02-034-3/+16
| | | | | | | | | | needed to emit a 64-bit gp-relative relocation entry. Make changes necessary for emitting jump tables which have entries with directive .gpdword. This patch does not implement the parts needed for direct object emission or JIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149668 91177308-0d34-0410-b5e6-96231b3b80d8
* Incorporate suggestions Chad, Jakob and Evan's suggestions on r149957.Lang Hames2012-02-031-22/+33
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149655 91177308-0d34-0410-b5e6-96231b3b80d8
* Require non-NULL register masks.Jakob Stoklund Olesen2012-02-021-2/+2
| | | | | | | It doesn't seem worthwhile to give meaning to a NULL register mask pointer. It complicates all the code using register mask operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149646 91177308-0d34-0410-b5e6-96231b3b80d8
* Add pseudo-registers for pairs, triples, and quads of D registers.Jakob Stoklund Olesen2012-02-021-15/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | NEON loads and stores accept single and double spaced pairs, triples, and quads of D registers. This patch adds new register classes to accurately model those constraints: Dn, Dn+1 Dn, Dn+2 ---------------------- DPair DPairSpc DTriple DTripleSpc DQuad DQuadSpc Also extend the existing QQ and QQQQ register classes to contains all Q pairs and quads instead of just the aligned ones. These new register classes will make it possible to accurately model constraints on NEON loads and stores, and we can get rid of all the NEON pseudo-instructions. The late scheduler will be able to accurately model instruction dependencies from the explicit operands. This more than doubles the number of ARM registers, but the backend passes are quite good at handling this. The llc -O0 compile time only regresses by 1.5%. Future work on register mask operands will recover this regression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149640 91177308-0d34-0410-b5e6-96231b3b80d8
* Minor change in signature of the getZeroVector() Elena Demikhovsky2012-02-021-30/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149601 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimization for SIGN_EXTEND operation on AVX.Elena Demikhovsky2012-02-024-0/+67
| | | | | | | | | Special handling was added for v4i32 -> v4i64 and v8i16 -> v8i32 extensions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149600 91177308-0d34-0410-b5e6-96231b3b80d8
* Unbreak the MSVC build.Francois Pichet2012-02-021-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149599 91177308-0d34-0410-b5e6-96231b3b80d8
* Set EFLAGS correctly in EmitLoweredSelect on X86.Lang Hames2012-02-021-2/+29
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149597 91177308-0d34-0410-b5e6-96231b3b80d8
* Set the correct stack pointer register.Akira Hatanaka2012-02-021-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149585 91177308-0d34-0410-b5e6-96231b3b80d8
* Expand EHSELECTION and EHSELECTION nodes. Set the correct exception pointer andAkira Hatanaka2012-02-021-2/+4
| | | | | | | | selector registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149584 91177308-0d34-0410-b5e6-96231b3b80d8
* Add DWARF numbers of 64-bit registers.Akira Hatanaka2012-02-021-64/+64
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149583 91177308-0d34-0410-b5e6-96231b3b80d8
* Fix the cmake buildRafael Espindola2012-02-011-0/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149561 91177308-0d34-0410-b5e6-96231b3b80d8
* Instruction scheduling itinerary for Intel Atom.Andrew Trick2012-02-0115-514/+1016
| | | | | | | | | | | | | | Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
* Move ARM subreg index compositions to the SubRegIndex itself.Jakob Stoklund Olesen2012-02-011-28/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149557 91177308-0d34-0410-b5e6-96231b3b80d8
* Avoid creating an extract element to an illegal type after LegalizeTypes has ↵Mon P Wang2012-02-011-2/+10
| | | | | | run. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149548 91177308-0d34-0410-b5e6-96231b3b80d8
* VLIW specific scheduler framework that utilizes deterministic finite ↵Andrew Trick2012-02-015-0/+42
| | | | | | | | | | automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149547 91177308-0d34-0410-b5e6-96231b3b80d8
* Tidy up.Chad Rosier2012-02-011-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149521 91177308-0d34-0410-b5e6-96231b3b80d8
* Passing AVX 256-bit structures in Win64 was wrong.Elena Demikhovsky2012-02-011-0/+4
| | | | | | | | Fixed Win64 calling conventions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149494 91177308-0d34-0410-b5e6-96231b3b80d8
* Shortened code in shuffle masksElena Demikhovsky2012-02-011-33/+11
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149493 91177308-0d34-0410-b5e6-96231b3b80d8
* Optimization for "truncate" operation on AVX.Elena Demikhovsky2012-02-012-0/+101
| | | | | | | Truncating v4i64 -> v4i32 and v8i32 -> v8i16 may be done with set of shuffles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149485 91177308-0d34-0410-b5e6-96231b3b80d8
* SwitchInst refactoring.Stepan Dyatkovskiy2012-02-012-4/+4
| | | | | | | | | | | | | | | | | | | | The purpose of refactoring is to hide operand roles from SwitchInst user (programmer). If you want to play with operands directly, probably you will need lower level methods than SwitchInst ones (TerminatorInst or may be User). After this patch we can reorganize SwitchInst operands and successors as we want. What was done: 1. Changed semantics of index inside the getCaseValue method: getCaseValue(0) means "get first case", not a condition. Use getCondition() if you want to resolve the condition. I propose don't mix SwitchInst case indexing with low level indexing (TI successors indexing, User's operands indexing), since it may be dangerous. 2. By the same reason findCaseValue(ConstantInt*) returns actual number of case value. 0 means first case, not default. If there is no case with given value, ErrorIndex will returned. 3. Added getCaseSuccessor method. I propose to avoid usage of TerminatorInst::getSuccessor if you want to resolve case successor BB. Use getCaseSuccessor instead, since internal SwitchInst organization of operands/successors is hidden and may be changed in any moment. 4. Added resolveSuccessorIndex and resolveCaseIndex. The main purpose of these methods is to see how case successors are really mapped in TerminatorInst. 4.1 "resolveSuccessorIndex" was created if you need to level down from SwitchInst to TerminatorInst. It returns TerminatorInst's successor index for given case successor. 4.2 "resolveCaseIndex" converts low level successors index to case index that curresponds to the given successor. Note: There are also related compatability fix patches for dragonegg, klee, llvm-gcc-4.0, llvm-gcc-4.2, safecode, clang. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149481 91177308-0d34-0410-b5e6-96231b3b80d8
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