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* AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.Elena Demikhovsky2013-10-093-36/+92
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192283 91177308-0d34-0410-b5e6-96231b3b80d8
* AArch64: enable MISched by default.Tim Northover2013-10-091-0/+4
| | | | | | | | | | | | Substantial SelectionDAG scheduling is going away soon, and is interfering with Hao's attempts to implement LDn/STn instructions, so I say we make the leap first. There were a few reorderings (inevitably) which broke some tests. I tried to replace them with CHECK-DAG variants mostly, but some too complex for that to be useful and I just reordered them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192282 91177308-0d34-0410-b5e6-96231b3b80d8
* Add missing HasAVX512 predicate.Andrew Trick2013-10-091-2/+2
| | | | | | | This was only working because AVX had cheaper rules in all cases. I'm sure there are other places in this file where predicates are missing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192276 91177308-0d34-0410-b5e6-96231b3b80d8
* Replace a couple instructions with patterns referring to other instructions ↵Craig Topper2013-10-091-16/+11
| | | | | | with same encoding and operands. Mark a couple other instructions as CodeGenOnly since we have FR and VR instructions and only one of them is needed by the assembler/disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192274 91177308-0d34-0410-b5e6-96231b3b80d8
* Use AVX512PIi8 for the alt forms of vcmp instructions. This adds the TB ↵Craig Topper2013-10-091-4/+4
| | | | | | prefix and keeps the mnemonic from starting with an extra 'v' git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192272 91177308-0d34-0410-b5e6-96231b3b80d8
* Mark some instructions as CodeGenOnly since they aren't needed by the ↵Craig Topper2013-10-091-65/+73
| | | | | | assembler or disassembler. Disassembler already filtered them, but asm parser still had them in its tables. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192271 91177308-0d34-0410-b5e6-96231b3b80d8
* Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. ↵Craig Topper2013-10-093-8/+12
| | | | | | This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192266 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar floating-point reciprocal estimate,Chad Rosier2013-10-081-10/+34
| | | | | | reciprocal exponent, and reciprocal square root estimate instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192242 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar signed/unsigned integer to floating-pointChad Rosier2013-10-082-0/+52
| | | | | | convert instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192231 91177308-0d34-0410-b5e6-96231b3b80d8
* Add fabsf to the list of inlined functions; otherwiseReed Kotler2013-10-081-0/+1
| | | | | | | | | Mips16 will try and create a stub for it and this will result in a link error because that function does not exist in libc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192223 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Simplify and optimize code.Akira Hatanaka2013-10-082-11/+7
| | | | | | | No intended functionality change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192213 91177308-0d34-0410-b5e6-96231b3b80d8
* Let rotr and bswap be handled by expansion for Mips16 since we don'tReed Kotler2013-10-081-0/+5
| | | | | | | | have native instructions for this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192207 91177308-0d34-0410-b5e6-96231b3b80d8
* Add a MCTargetStreamer interface.Rafael Espindola2013-10-0819-139/+400
| | | | | | | | | | | | | This patch fixes an old FIXME by creating a MCTargetStreamer interface and moving the target specific functions for ARM, Mips and PPC to it. The ARM streamer is still declared in a common place because it is used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are completely hidden in the corresponding Target directories. I will send an email to llvmdev with instructions on how to use this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192181 91177308-0d34-0410-b5e6-96231b3b80d8
* SparcJITInfo.cpp: Prune "default:" label to fix a warning. ↵NAKAMURA Takumi2013-10-081-1/+0
| | | | | | [-Wcovered-switch-default] git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192179 91177308-0d34-0410-b5e6-96231b3b80d8
* Prune trailing linefeeds.NAKAMURA Takumi2013-10-081-2/+0
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192178 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Implement JIT for SPARC.Venkatraman Govindaraju2013-10-0812-44/+586
| | | | | | | | | No new testcases. However, this patch makes all supported JIT testcases in test/ExecutionEngine pass on Sparc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192176 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unneeded MMX instruction definition by moving pattern to an ↵Craig Topper2013-10-081-6/+2
| | | | | | equivalent instruction definition and removing the filtering from the disassembler table building. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192175 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some instructions that existed to provide aliases to the assembler. ↵Craig Topper2013-10-081-27/+10
| | | | | | Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192171 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Do not hardcode nop in the delay slot of TLS_CALL. Use ↵Venkatraman Govindaraju2013-10-082-3/+4
| | | | | | DelaySlotFiller to fill the delay slot instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192160 91177308-0d34-0410-b5e6-96231b3b80d8
* Add Mips16 patterns for sign extend byte and sign extend halfword.Reed Kotler2013-10-071-0/+30
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192130 91177308-0d34-0410-b5e6-96231b3b80d8
* Struct byval: use the correct alignment for loads generated to loadManman Ren2013-10-071-1/+2
| | | | | | | | | | | | | | | | from struct byval to registers. We used to pass 0 which means the alignment of PtrVT. Even when the alignment of the struct is smaller than 4, the LOADs would have alignment of 4, and further optimizations could combine the LOADs into a ldm, which would cause crash. The fix is to pass the alignment of the struct byval. rdar://problem/15144402 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192126 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Coding style clean up.Akira Hatanaka2013-10-072-62/+46
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192125 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Disable tail merging when long branch pass is enabled.Akira Hatanaka2013-10-071-1/+7
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192124 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Fix type check. Just because an integer type is illegal doesn't mean ↵Benjamin Kramer2013-10-071-1/+1
| | | | | | | | | it's i64. Fixes PR17495, where an i24 triggered this code. It's intended to optimize i64 loads on 32 bit x86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192123 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Define method MipsSubtarget::enableLongBranchPass.Akira Hatanaka2013-10-072-2/+5
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192122 91177308-0d34-0410-b5e6-96231b3b80d8
* [mips] Fix definition of mfhi and mflo instructions to read from the wholeAkira Hatanaka2013-10-0710-79/+105
| | | | | | | | | | | | | | | | | accumulator instead of its sub-registers, $hi and $lo. We need this change to prevent a mflo following a mtlo from reading an unpredictable/undefined value, as shown in the following example: mult $6, $7 // result of $6 * $7 is written to $lo and $hi. mflo $2 // read lower 32-bit result from $lo. mtlo $4 // write to $lo. the content of $hi becomes unpredictable. mfhi $3 // read higher 32-bit from $hi, which has an unpredictable value. I don't have a test case for this change that reliably reproduces the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192119 91177308-0d34-0410-b5e6-96231b3b80d8
* [ARM] Improve build attributes emission.Amara Emerson2013-10-076-56/+91
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192111 91177308-0d34-0410-b5e6-96231b3b80d8
* [AArch64] Add support for NEON scalar arithmetic instructions:Chad Rosier2013-10-072-44/+141
| | | | | | SQDMULH, SQRDMULH, FMULX, FRECPS, and FRSQRTS. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192107 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove getEHExceptionRegister and getEHHandlerRegister.Rafael Espindola2013-10-0712-72/+0
| | | | | | They haven't been used for a long time. Patch by MathOnNapkins. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192099 91177308-0d34-0410-b5e6-96231b3b80d8
* ARM: allow cortex-m0 to use hint instructionsTim Northover2013-10-075-9/+22
| | | | | | | | | | | The hint instructions ("nop", "yield", etc) are mostly Thumb2-only, but have been ported across to the v6M architecture. Fortunately, v6M seems to sit nicely between v6 (thumb-1 only) and v6T2, so we can add a feature for it fairly easily. rdar://problem/15144406 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192097 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some instructions that seem to only exist to trick the filtering ↵Craig Topper2013-10-071-12/+0
| | | | | | checks in the disassembler table creation. Just fix up the filter to let the real instruction through instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192090 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove FsMOVAPSrr and friends. They have no patterns and are no longer ↵Craig Topper2013-10-072-29/+4
| | | | | | selected anywhere. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192089 91177308-0d34-0410-b5e6-96231b3b80d8
* Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to ↵Craig Topper2013-10-072-1/+50
| | | | | | | | | | register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not. This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192088 91177308-0d34-0410-b5e6-96231b3b80d8
* Add disassembler support for long encodings for INC/DEC in 32-bit mode.Craig Topper2013-10-071-1/+15
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192086 91177308-0d34-0410-b5e6-96231b3b80d8
* X86: Don't fold spills into SSE operations if the stack is unaligned.Benjamin Kramer2013-10-061-0/+4
| | | | | | | Regalloc can emit unaligned spills nowadays, but we can't fold the spills into SSE ops if we can't guarantee alignment. PR12250. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192064 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: added scalar convert instructions and intrinsics.Elena Demikhovsky2013-10-063-13/+189
| | | | | | | Fixed load folding in VPERM2I instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192063 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Do not emit nop after fcmp* instruction with V9.Venkatraman Govindaraju2013-10-062-7/+22
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192056 91177308-0d34-0410-b5e6-96231b3b80d8
* AVX-512: fixed shuffle loweringElena Demikhovsky2013-10-062-1/+15
| | | | | | | in case of BLEND and added VSHUFPS patterns. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192055 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Custom lower addc/adde/subc/sube on i64 in sparc64.Venkatraman Govindaraju2013-10-062-7/+55
| | | | | | | | This is required because i64 is a legal type but addxcc/subxcc reads icc carry bit, which are 32 bit conditional codes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192054 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Use addxcc/subxcc for adde/sube instead of addx/subx.Venkatraman Govindaraju2013-10-061-4/+4
| | | | | | | addx/subx does not modify conditional codes whereas addxcc/subxx does. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192053 91177308-0d34-0410-b5e6-96231b3b80d8
* Add TBM instructions to loading folding tables.Craig Topper2013-10-051-1/+21
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192046 91177308-0d34-0410-b5e6-96231b3b80d8
* Rename this feature to "cx16" to match gcc's flag name. Apparently these stringsNick Lewycky2013-10-051-1/+1
| | | | | | | are directly tied to the flag names in clang with no remapping in between? git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192044 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove underscores from TBM instruction names for consistency with other ↵Craig Topper2013-10-051-24/+24
| | | | | | instruction naming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192040 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns ↵Craig Topper2013-10-051-39/+20
| | | | | | are sufficient. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192039 91177308-0d34-0410-b5e6-96231b3b80d8
* Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into ↵Craig Topper2013-10-051-0/+6
| | | | | | (sub -2, x). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192037 91177308-0d34-0410-b5e6-96231b3b80d8
* Remove some really nasty uses of hasRawTextSupport.Rafael Espindola2013-10-0510-173/+125
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When MC was first added, targets could use hasRawTextSupport to keep features working before they were added to the MC interface. The design goal of MC is to provide an uniform api for printing assembly and object files. Short of relaxations and other corner cases, a object file is just another representation of the assembly. It was never the intention that targets would keep doing things like if (hasRawTextSupport()) Set flags in one way. else Set flags in another way. When they do that they create two code paths and the object file is no longer just another representation of the assembly. This also then requires testing with llc -filetype=obj, which is extremelly brittle. This patch removes some of these hacks by replacing them with smaller ones. The ARM flag setting is trivial, so I just moved it to the constructor. For Mips, the patch adds two temporary hack directives that allow the assembly to represent the same things as the object file was already able to. The hope is that the mips developers will replace the hack directives with the same ones that gas uses and drop the -print-hack-directives flag. I will also try to implement a target streamer interface, so that we can move this out of the common code. In summary, for any new work, two rules of the thumb are * Don't use "llc -filetype=obj" in tests. * Don't add calls to hasRawTextSupport. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192035 91177308-0d34-0410-b5e6-96231b3b80d8
* Implement aarch64 neon instruction set AdvSIMD (Across).Jiangning Liu2013-10-052-0/+144
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192028 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Use correct alignment while loading/storing fp128 values.Venkatraman Govindaraju2013-10-051-4/+13
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192023 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Respect hasHardQuad parameter correctly when lowering SINT_TO_FP ↵Venkatraman Govindaraju2013-10-051-1/+1
| | | | | | with fp128 operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192015 91177308-0d34-0410-b5e6-96231b3b80d8
* [Sparc] Correct the floating point conditional code mapping in ↵Venkatraman Govindaraju2013-10-041-8/+8
| | | | | | GetOppositeBranchCondition(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192006 91177308-0d34-0410-b5e6-96231b3b80d8
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