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| * Implement ISD::VAARG lowering on PPC32.Roman Divacky2011-06-281-5/+123
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134005 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix cmake build.Rafael Espindola2011-06-281-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133989 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARM Thumb2 asm syntax optional destination operand for binary operators.Jim Grosbach2011-06-281-9/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the destination operand is the same as the first source register operand for arithmetic instructions, the destination operand may be omitted. For example, the following two instructions are equivalent: and r1, #ff and r1, r1, #ff rdar://9672867 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133973 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARM Assembly support for Thumb mov-immediate.Jim Grosbach2011-06-273-4/+40
| | | | | | | | | | | | | | | | | | | | | | | | Correctly parse the forms of the Thumb mov-immediate instruction: 1. 8-bit immediate 0-255. 2. 12-bit shifted-immediate. The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic, but is not yet supported. More parser logic necessary there due to fixups. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133966 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARM Asm parsing of Thumb2 move immediate.Jim Grosbach2011-06-271-2/+3
| | | | | | | | | | | | | | Thumb2 MOV mnemonic can accept both cc_out and predication. We don't (yet) encode the instruction properly, but this gets the parsing part. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133945 91177308-0d34-0410-b5e6-96231b3b80d8
| * More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-276-29/+28
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133944 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add exception necessitated by 133938.Jim Grosbach2011-06-271-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133939 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARM assembly carry set/clear condition code aliases for 'hi/lo'Jim Grosbach2011-06-271-0/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133938 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARM assembler support for ldmfd/stmfd mnemonics.Jim Grosbach2011-06-271-0/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133936 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARM assembler support for vpush/vpop.Jim Grosbach2011-06-271-0/+9
| | | | | | | | | | | | | | | | | | | | | | Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple writeback instructions w/ SP as the base pointer. rdar://9683231 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133932 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARM Assembly syntax support for arithmetic implied dest operand.Jim Grosbach2011-06-271-7/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the destination operand is the same as the first source register operand for arithmetic instructions, the destination operand may be omitted. For example, the following two instructions are equivalent: sub r2, r2, #6 sub r2, #6 rdar://9682597 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133925 91177308-0d34-0410-b5e6-96231b3b80d8
| * Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-2768-121/+130
| | | | | | | | | | | | | | into XXXGenRegisterInfo.inc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133922 91177308-0d34-0410-b5e6-96231b3b80d8
| * Grow the X86FloatingPoint register map to hold 16 registers.Jakob Stoklund Olesen2011-06-271-5/+15
| | | | | | | | | | | | | | This allows for more live scratch registers which is needed to handle live ST registers before return and inline asm instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133903 91177308-0d34-0410-b5e6-96231b3b80d8
| * Replace dyn_cast<> with cast<> since the cast is already guarded by the ↵Chad Rosier2011-06-251-1/+1
| | | | | | | | | | | | necessary check. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133874 91177308-0d34-0410-b5e6-96231b3b80d8
| * PTX: Reverting implementation of i8.Dan Bailey2011-06-257-296/+73
| | | | | | | | | | | | | | | | | | | | The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support boolean values. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133873 91177308-0d34-0410-b5e6-96231b3b80d8
| * Enable tail call optimization in the presence of a byval (x86-32 and x86-64).Chad Rosier2011-06-251-0/+4
| | | | | | | | | | | | <rdar://problem/9483883> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133858 91177308-0d34-0410-b5e6-96231b3b80d8
| * Unbreak CMake buildDouglas Gregor2011-06-251-0/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133853 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add include guard.Evan Cheng2011-06-241-0/+5
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133847 91177308-0d34-0410-b5e6-96231b3b80d8
| * Rename TargetDesc to MCTargetDescEvan Cheng2011-06-246-4/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133846 91177308-0d34-0410-b5e6-96231b3b80d8
| * Refactor MachO relocation generaration into the Target directories.Jim Grosbach2011-06-243-0/+885
| | | | | | | | | | | | | | | | | | | | Move the target-specific RecordRelocation logic out of the generic MC MachObjectWriter and into the target-specific object writers. This allows nuking quite a bit of target knowledge from the supposedly target-independent bits in lib/MC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133844 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix cmake build.Rafael Espindola2011-06-241-0/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133830 91177308-0d34-0410-b5e6-96231b3b80d8
| * Hoist simple check above more complex checking to avoid unnecessary Chad Rosier2011-06-241-5/+5
| | | | | | | | | | | | | | overheads. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133824 91177308-0d34-0410-b5e6-96231b3b80d8
| * - Add MCRegisterInfo registration machinery. Also added x86 registration ↵Evan Cheng2011-06-242-0/+16
| | | | | | | | | | | | | | | | | | routines. - Rename TargetRegisterDesc to MCRegisterDesc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133820 91177308-0d34-0410-b5e6-96231b3b80d8
| * ARM movw/movt fixups need to mask the high bits.Jim Grosbach2011-06-241-3/+6
| | | | | | | | | | | | | | | | | | | | The fixup value comes in as the whole 32-bit value, so for the lo16 fixup, the upper bits need to be masked off. Previously we assumed the masking had already been done and asserted. rdar://9635991 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133818 91177308-0d34-0410-b5e6-96231b3b80d8
| * PTX: Add support for i8 type and introduce associated .b8 registersDan Bailey2011-06-247-15/+291
| | | | | | | | | | | | | | | | The i8 type is required for boolean values, but can only use ld, st and mov instructions. The i1 type continues to be used for predicates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133814 91177308-0d34-0410-b5e6-96231b3b80d8
| * The Neon VCVT (between floating-point and fixed-point, Advanced SIMD) Chad Rosier2011-06-241-1/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | instructions can be used to match combinations of multiply/divide and VCVT (between floating-point and integer, Advanced SIMD). Basically the VCVT immediate operand that specifies the number of fraction bits corresponds to a floating-point multiply or divide by the corresponding power of 2. For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a combination of VMUL and VCVT (floating-point to integer) as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vmul.f32 d16, d17, d16 vcvt.s32.f32 d16, d16 becomes: vcvt.s32.f32 d16, d16, #3 Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a combinations of VCVT (integer to floating-point) and VDIV as follows: Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>): vcvt.f32.s32 d16, d16 vdiv.f32 d16, d17, d16 becomes: vcvt.f32.s32 d16, d16, #3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133813 91177308-0d34-0410-b5e6-96231b3b80d8
| * PTX: Add preliminary support for outputting debug information in the form ofJustin Holewinski2011-06-241-0/+97
| | | | | | | | | | | | | | | | | | | | .file and .loc directives. Ideally, we would utilize the existing support in AsmPrinter for this, but I cannot find a way to get .file and .loc directives to print without the rest of the associated DWARF sections, which ptxas cannot handle. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133812 91177308-0d34-0410-b5e6-96231b3b80d8
| * Change the chain input of nodes that load the address of a function. This changeAkira Hatanaka2011-06-241-4/+1
| | | | | | | | | | | | | | | | | | | | | | enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a pre-existing node instead of redundantly create a new node every time it is called. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133811 91177308-0d34-0410-b5e6-96231b3b80d8
| * Prevent generation of redundant addiu instructions that compute address of Akira Hatanaka2011-06-241-1/+2
| | | | | | | | | | | | | | | | | | static variables or functions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133803 91177308-0d34-0410-b5e6-96231b3b80d8
| * PTX: Re-work target sm/compute selection and add some basic GPUJustin Holewinski2011-06-246-47/+121
| | | | | | | | | | | | targets: g80, gt200, gf100(fermi) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133799 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix CellSPU CMakeList.txt.Rafael Espindola2011-06-241-1/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133792 91177308-0d34-0410-b5e6-96231b3b80d8
| * Fix CellSPU CMakeLists.txtEvan Cheng2011-06-241-2/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133787 91177308-0d34-0410-b5e6-96231b3b80d8
| * Starting to refactor Target to separate out code that's needed to fully describeEvan Cheng2011-06-2444-104/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | target machine from those that are only needed by codegen. The goal is to sink the essential target description into MC layer so we can start building MC based tools without needing to link in the entire codegen. First step is to refactor TargetRegisterInfo. This patch added a base class MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to separate register description from the rest of the stuff. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add support for movntil/movntiq mnemonics. Reported on llvmdev.Eli Friedman2011-06-231-2/+2
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133759 91177308-0d34-0410-b5e6-96231b3b80d8
| * Rename TargetOptions::StackAlignment to StackAlignmentOverride.Evan Cheng2011-06-232-3/+3
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133739 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove TargetOptions.h dependency from ARMSubtarget.Evan Cheng2011-06-232-5/+4
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133738 91177308-0d34-0410-b5e6-96231b3b80d8
| * PTX: Always use registers for return values, but use .param space for deviceJustin Holewinski2011-06-236-108/+725
| | | | | | | | | | | | | | | | | | | | | | parameters if SM >= 2.0 - Update test cases to be more robust against register allocation changes - Bump up the number of registers to 128 per type - Include Python script to re-generate register file with any number of registers git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
| * PTX: Whitespace fixes and remove commented out codeJustin Holewinski2011-06-232-36/+0
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133734 91177308-0d34-0410-b5e6-96231b3b80d8
| * PTX: Prevent DCE from eliminating st.param calls, and unify the handling ofJustin Holewinski2011-06-235-107/+78
| | | | | | | | | | | | | | | | st.param and ld.param FIXME: Test cases still need to be updated git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133733 91177308-0d34-0410-b5e6-96231b3b80d8
| * PTX: Use .param space for parameters in device functions for SM >= 2.0Justin Holewinski2011-06-236-33/+126
| | | | | | | | | | | | FIXME: DCE is eliminating the final st.param.x calls, figure out why git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133732 91177308-0d34-0410-b5e6-96231b3b80d8
| * Remove TargetOptions.h dependency from X86Subtarget.Evan Cheng2011-06-236-42/+46
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133726 91177308-0d34-0410-b5e6-96231b3b80d8
* | Merge upstream to r133718, Fri. 24th June 2011.Nowar Gu2011-06-242-2/+0
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| * CppBackend: fixup for api changeDylan Noblesmith2011-06-231-1/+0
| | | | | | | | | | | | | | | | This broke after r133364. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133709 91177308-0d34-0410-b5e6-96231b3b80d8
| * Reinstate r133513 (reverted in r133700) with an additional fix for aJay Foad2011-06-231-1/+1
| | | | | | | | | | | | | | -Wshorten-64-to-32 warning in Instructions.h. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133708 91177308-0d34-0410-b5e6-96231b3b80d8
| * Revert r133513:Eric Christopher2011-06-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | "Reinstate r133435 and r133449 (reverted in r133499) now that the clang self-hosted build failure has been fixed (r133512)." Due to some additional warnings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133700 91177308-0d34-0410-b5e6-96231b3b80d8
| * Use the presence of the __compact_unwind section to indicate that a targetBill Wendling2011-06-231-1/+0
| | | | | | | | | | | | | | supports compact unwind info instead of having a separate flag indicating this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133685 91177308-0d34-0410-b5e6-96231b3b80d8
* | Fix source list of Android.mk.Nowar Gu2011-06-231-0/+1
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* | Merge upstream to r133679 at Thu. 23th Jun 2011.Nowar Gu2011-06-2340-561/+728
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| * Get rid of one getStackAlignment(). RegisterInfo shouldn't need to know ↵Evan Cheng2011-06-233-11/+8
| | | | | | | | | | | | about stack alignment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133679 91177308-0d34-0410-b5e6-96231b3b80d8
| * Add a flag that indicates whether a target supports compact unwind info or not.Bill Wendling2011-06-221-0/+1
| | | | | | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133662 91177308-0d34-0410-b5e6-96231b3b80d8
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